Browse Prior Art Database

THUNDERBOLT BUFFERED DRIVER CONTROLLER DESIGN

IP.com Disclosure Number: IPCOM000008521D
Original Publication Date: 1997-Dec-01
Included in the Prior Art Database: 2002-Jun-19
Document File: 2 page(s) / 113K

Publishing Venue

Motorola

Related People

Scott Chiu: AUTHOR [+2]

Abstract

This circuit arbitrates video display memory access between a low power Motorola micro- controller running at parity speed with the display (about 800K Hz) and the display refresh mecha- nism. Because of the displays need to be constantly refreshed, and the low speed of the processor, it is virtually impossible to guarantee access to the video memory for data refresh. This mechanism would permit such access without increasing clock speed or putting the micro-controller into wait states which might cause it to miss a service interrupt such as a page or other real time radio service request. At the same time, this design works equally well with a conventional low-cost SRAM.

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MOTOROLA Technical Developments

THUNDERBOLT BUFFERED DRIVER CONTROLLER DESIGN

by Scott Chiu and Scott Novis

DESCRIPTION

  This circuit arbitrates video display memory access between a low power Motorola micro- controller running at parity speed with the display (about 800K Hz) and the display refresh mecha- nism. Because of the displays need to be constantly refreshed, and the low speed of the processor, it is virtually impossible to guarantee access to the video memory for data refresh. This mechanism would permit such access without increasing clock speed or putting the micro-controller into wait states which might cause it to miss a service interrupt such as a page or other real time radio service request. At the same time, this design works equally well with a conventional low-cost SRAM.

PROBLEM STATEMENT

  Most conventional display driver memory arbi- tration mechanisms make several assumptions which are not valid with either a zero persistence display (such as an LED emmissive display like thunderbolt) or the host processor speed and bus architecture. Specifically they assume it is accept- able to halt the processor while waiting for memory access, or that the display refresh can be interrupted, or that the processor runs significantly faster than the display refresh hardware. None of these assumptions are true for a Thunderbolt based pager.

INNOVATION

  The addition of an 8 byte character buffer within the controller and synchronization circuitry which allow the micro-controller to write to the video memory as if it were a modified parallel buffered UART-Universal Asynchronous Receiver Transmitter. The addition of this buffer allows micro-controller read and write cycles to be synchronized using the display segmented refresh counter. The new structure enables a system design

using very low clock speeds where the displayed data can be updated without blanking or intemtpting the refresh of the screen.

DESIGN OVERVIEW

  The main function of this module is to perform the function of arbitration between a load balanced Micro-controller or CPU, and a display. The key elements of this design are the control status regis-

ter block, an internal 8 byte graphics buffer, and internal segmented refresh logic. The control status register block (CSRB) consists of a 16 bit interface. The CSRB has an 8 bit bidirectional data bus inter- face which provides pass through to the internal S-byte character buffer, or depending upon control logic state, pass through to an external graphics display RAM. This bus can be attached dire...