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Method for a content-aware bridge

IP.com Disclosure Number: IPCOM000008561D
Publication Date: 2002-Jun-24
Document File: 3 page(s) / 63K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a content-aware bridge. Benefits include improved performance.

This text was extracted from a Microsoft Word document.
This is the abbreviated version, containing approximately 44% of the total text.

Method for a content-aware bridge

Disclosed is a method for a content-aware bridge. Benefits include improved performance.

Background

              Latency can be a throughput-limiting factor for high-speed I/O devices. Peripheral bus read accesses are high-latency operations because the bridge cannot immediately satisfy the request. The bridge must first retrieve the requested data from memory. For high-speed I/O devices, such as 10- or 40-gigabit Ethernet media access controllers (MACs), these latencies can significantly hamper performance.

              Push interfaces avoid the latencies of read operations by using writes exclusively. However, push interfaces can also induce latencies. The primary latency is due to the host driver monitoring first-in-first-out (FIFO) buffer fullness levels to avoid overruns on the target devices. To avoid underruns and underutilize the device, the driver must be informed when FIFO buffer levels are low so that new commands can be issued to the device. The device generally informs the driver of these low states with interrupts. Interrupts often have significant latencies associated with them. For optimal overall system performance, the rate of interrupt generation from a device is typically limited. In some operating systems, interrupt processing is not conducted in the interrupt service routine (ISR) but is handled later in a deferred procedure call (DPC), which adds latencies to interrupt processing.

              A requirement exists for a method that enables a peripheral device to master data and commands when they are requested and for the peripheral bus to be able to supply the requested data with little or no latency.

              Conventional I/O controllers typically use descriptors for the hardware-software interface. These descriptors are referred to as scatter-gather descriptors or direct memory access (DMA) descriptors. These descriptors contain information that the device requires to master data for I/O operations across the bus. This information includes the memory address and length information to access the data and control information about how the data should be processed, such as offload operations that must be performed.

              For example, the MAC reads these descriptors and then accesses the memory addresses referred to in the buffer address field of the descriptors. Conventionally, this read access is likely to incur significant latencies. The descriptor reads are initiated by the device driver writing to a control register to inform the MAC that more descriptors are ready to be processed. An overview of the conventional flow includes the following steps:

1.      Driver writes to descriptor control register.

2.      Device reads descriptor(s).

3.      Device reads data referred to by the descriptor(s).

4.      Device operates on the data.

General description

              The disclosed method enables the peripheral bus bridge chipset to predict and prepare for future bus transactions based on previous bus transactions. This approach enables the device requests to be fulfilled...