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Method for wordline-tracking ATD delay

IP.com Disclosure Number: IPCOM000008562D
Publication Date: 2002-Jun-24
Document File: 2 page(s) / 100K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for wordline-tracking adaptive threshold detector (ATD) delay. Benefits include improved performance and an improved design/validation environment.

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Method for wordline-tracking ATD delay

Disclosed is a method for wordline-tracking adaptive threshold detector (ATD) delay. Benefits include improved performance and an improved design/validation environment.

Background

              ATD combats process mismatch between arrays and periphery. A requirement exists for ATD to work under all conditions, including process variation, voltage supply, and temperature. Parts must be optimized, which requires a delay three times longer than for the conventional case, even though the additional delay extends access time beyond the customer specification.

Description

              The disclosed method is ATD and a wordline-tracking mechanism. It is comprised of a rising-edge triggered D flip-flop, a dummy wordline from the array, and some glue-logic. Positive-channel metal oxide semiconductor (PMOS) devices are anchored at the end of each wordline to pull the signal up to the supply quickly for retriggering (see Figure 1). A waveform explains the internal signals and how the circuit operates (see Figure 2).

              The circuit enables ATD to trim itself to the array to eliminate any mismatch, save design and validation time, and meet the commitment to the customer by successfully achieving the access-time specification. This self-trimming eliminates the problem of extending the delay past the access time and reaching aggressive speed targets.

              A similar architecture is used to match the delay on the differential sensing bus. A dummy parasitic route of exact length is used...