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Method for enabling at speed, back-to-back system cycle-based transition tests using a slow external clock

IP.com Disclosure Number: IPCOM000008571D
Publication Date: 2002-Jun-24
Document File: 4 page(s) / 142K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for enabling at speed, back-to-back system cycle-based transition tests using a slow external clock. Benefits include an improved test environment.

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Method for enabling at speed, back-to-back system cycle-based transition tests using a slow external clock

Disclosed is a method for enabling at speed, back-to-back system cycle-based transition tests using a slow external clock. Benefits include an improved test environment.

Background

              In automated test program generator (ATPG) testing, the tester must take control of the functional and scan clocks of the device under test (DUT). The tester must also have access to the DUT scan chains. For the ATPG test to run at speed, the tester must run at clock speeds that are equal to or higher than the internal clock speed of the DUT. This poses a logistical problem as testers’ clock speeds are falling behind the DUT internal clock speeds. High-speed testers are prohibitively expensive.

General description

              The disclosed method enables at-speed testing (transition fault test) of a semiconductor device when the tester clock runs at a substantially lower speed than the DUT’s clock frequency. The slow tester clock can be asynchronous to the DUT internal faster clock with no compromise to the transition test robustness. The disclosed method results in a better at-speed test at a significantly lower test cost because it eliminates the requirement to buy expensive testers that can run at the DUT internal clock speed.

Advantages

              The disclosed method provides advantages including:

·        Enables low-cost slow testers to be used for the purpose of delay (transition) testing, providing a mechanism to apply at-speed tests within the test budget

·        Reduces/eliminates reliance on accurate edge-placement and high-speed clocks from the tester, reducing the cost of test equipment

·        Enables broadside (back-to-back) delay tests by using an external slow tester signal to initiate a burst of back-to-back functional clock signals at core clock speed inside the microprocessor

Detailed description

              The disclosed method solves the tester speed problem by embedding a circuit that uses a slow asynchronous tester clock signal to generate an at-speed launch and capture system clock pulse. It is derived from the DUT’s own internal clock (MCLK).

              The functional clock control logic (FCCL) is programmable to ge...