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Method for enabling at-speed skewed-load transition testing using a slow external clock

IP.com Disclosure Number: IPCOM000008572D
Publication Date: 2002-Jun-24
Document File: 4 page(s) / 186K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for enabling at-speed skewed-load transition testing using a slow external clock. Benefits include an improved, cost effective test environment.

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Method for enabling at-speed skewed-load transition testing using a slow external clock

Disclosed is a method for enabling at-speed skewed-load transition testing using a slow external clock. Benefits include an improved, cost effective test environment.

Background

              A design must be verified that it is functionally/logically correct. It also must be verified for functionality at the rated clock speed. One test for this functionality is transition testing. A transition is initiated at an internal node of a circuit and then captured at a latch or a flip-flop at a speed as close to the core clock speed as possible (subject to design constraints). The two prerequisites for a transition test are: a mechanism to launch a transition, and a mechanism to capture the response within the desired clocking window.

Description

              The disclosed method is a scan-based transition test mechanism called skewed-load, which is applied to transition tests.

              A skewed-load transition test consists of the following steps:

1.      Load up the scan chain using a regular shift vector.

2.      Apply an additional shift cycle. Due to this additional shift, scan cells that change value during the additional shift (due to a different value sitting in an adjacent scan chain element) become sources of transitions (launch points). Additionally, this operation initiates transitions in internal nodes of the circuit.

3.      Generate a system clock to capture the response of the circuit to the transition. The window between the last shift (Step 2) and the system clock must be carefully timed so that the circuit response is captured within the at-speed window.

              Step 3 may be optionally followed by additional capture clocks to propagate the circuit response to observable points (scan cells).

              The circuitry that enables the signal shift lock and the capture clock in a tightly timed window is part of the disclosed method.

              A timing diagram (see Figure 1) shows a skewed load transition test that consists of the following steps:

1.      A normal scan operation consists of ACLK-BCLK sequences ending in BCLK.

2.      An additional ACLK pulse (shown as ACLK*) is launched in response to an internally generated signal, called LAUNCH_PULSE.

3.      After issuing the ACLK* pulse, each master scan latch gets the value in...