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Method for Seamlessly Scaling Multiple Image Processors

IP.com Disclosure Number: IPCOM000008574D
Publication Date: 2002-Jun-24
Document File: 6 page(s) / 7M

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a capture interface to scale multiple GILA chips and achieve a high throughput rate or process a larger image. Benefits include scalability while minimizing the impact to the current architecture.

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Method for Seamlessly Scaling Multiple Image Processors

Disclosed is a method for a capture interface to scale multiple GILA chips and achieve a high throughput rate or process a larger image. Benefits include scalability while minimizing the impact to the current architecture.

General Description

Theory of Operation

To achieve a higher throughput rate, the disclosed method splits up the incoming pixel stream and has more than one GILA chip operating on the image at a time. Figure 1 shows how an incoming image can be divided in half. Each half is processed by a different GILA chip. Figure 2 show the two GILA chip interconnectivity.

Note. Overlap occurs when more than one GILA is processing an image, thereby reducing the overall efficiency. There are methods to reduce the amount of overlap, but this disclosure does not discuss these options.

Parallel processing is accomplished by enhancing the current GILA interface with a programmable pixel counting mechanism. This new capture interface captures a different image width dependent upon the configuration it is used in (see Figure 3). The pixel counter has a programmable "Start" and "Stop" pixel count value. Each GILA counts all pixels being transmitted by the scan head, but only captures the pixels which lie within the "Start" and "Stop" window. Additionally, a TOKEN ring configuration between the multiple chips provides system level syncing between all chips. This provides the ability for the capture interface of any GILA to re-sync itself if it falls out of synchronization with other GILAs.

The capture interface can also generate an interrupt after a finite number of lines have been captured. This interrupt can be used to kick off following processes. Referring to Figures 1 and 2, the registers in each GILA is programmed as follows:

§         GILA 1: Start 0                                  Stop 3500

§         GILA 2: Start 3200                    Stop 6600

Since "Start" and "Stop" are programmable, overlap between the two GILAs can be adjusted to accommodate the application. Figures 4 and 5 represent the four GILA chip approach.

Performance Estimates

GILA performance estimates to date have been based on a given set of variables which include, but are not limited to: a given inter-page gap, clock rate, algorithm subset, SDRAM b...