Browse Prior Art Database

TVS/ESD PROTECTION USING A ZENER SOLUTION FOR MULTIPLE BUS LINES AND CAPACITANCES

IP.com Disclosure Number: IPCOM000008577D
Original Publication Date: 1998-Mar-01
Included in the Prior Art Database: 2002-Jun-25
Document File: 2 page(s) / 80K

Publishing Venue

Motorola

Related People

Scott N. Whitt: AUTHOR

Abstract

A cost effective solution for protecting multiple bus lines against potential TVS or ESD surges is the dual bi-directional common cathode zener diode in the SOT-223 package (Figure I). The part has a minimum power dissipation of 200W and can be manufactured in various voltages (5-50 V) and capacitances (50-500 pF).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

MOTOROLA Technical Developments

TIWESD PROTECTION USING A ZENER SOLUTION FOR MULTIPLE BUS LINES AND CAPACITANCES

by Scott N. Whitt

ABSTRACT

  A cost effective solution for protecting multiple bus lines against potential TVS or ESD surges is the dual bi-directional common cathode zener diode in the SOT-223 package (Figure I). The part has a minimum power dissipation of 200W and can be manufactured in various voltages (5-50 V) and capacitances (50-500 pF).

  In conjunction with Delco Electronics, OSPD marketing, and OSPD product engineering (Simon Keeton) , the zener development team (Scott Whitt, Bill Gandy, Jerry Quah) was approached with the opportunity to design a device for a TVS applica- tion The particular application required the zener diode to protect two communication bus lines against a IO/l000 ps exponential waveform as well as a 25,000 V ESD surge. In addition the customer wanted the ASP for this part to be equal to or below that of three comparable zener diodes.

DESCRIPTION

  The device uses planar technology in three masking layers (Figure 2). Thermal oxide is grown on a boron doped silicon substrate whose specific resistivity governs the targeted breakdown voltage. Layer one opens up the three junction regions and

the channel stop around each region to inhibit sttr- face inversion, Phosphorus is then implanted and then redistributed into the substrate to form the required doping profile. Layer two targets the capacitance of the device by manipulating the...