Browse Prior Art Database

HIGH BANDWIDTH FAST SETTLING TIME OPERATIONAL AMPLIFIER AND METHOD THEREFOR

IP.com Disclosure Number: IPCOM000008578D
Original Publication Date: 1998-Mar-01
Included in the Prior Art Database: 2002-Jun-25
Document File: 3 page(s) / 157K

Publishing Venue

Motorola

Related People

Matthew Miller: AUTHOR [+2]

Abstract

Operational amplifiers are commonly used in switched capacitor circuits because they have an extremely high or infinite input impedance, a large differential voltage gain, and a high gain bandwidth to insure a fast settling time.

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m MOTOROLA Technical Developments

HIGH BANDWIDTH FAST SETTLING TIME OPERATIONAL AMPLIFIER AND METHOD THEREFOR

by Matthew Miller and Andrew Pagones

  Operational amplifiers are commonly used in switched capacitor circuits because they have an extremely high or infinite input impedance, a large differential voltage gain, and a high gain bandwidth to insure a fast settling time.

  Figure 1 is a schematic diagram of an opera- tional amplifier 61 that includes an input IN+, an input IN-, an output Vo+, and an output Vo-. Operational amplifier 61 comprises a first stage and

a second stage. The first stage comprises transistors 62 and 63, resistors 64 and 65, and a current source
66. Transistors 62 and 63 are enhancement IGFETs (Insulated Gate Field Effect Transistors) in a source follower configuration having a drain, gate, source, and bulk corresponding to a first electrode, a control electrode, a second electrode, and a bulk terminal. In the embodiment illustrated in Figure I, transis- tors 62 and 63 are p-channel devices. The second stage comprises an amplification stage 67.

"DD

61

J

rh

65

64.

/

67

I I I

A 0

69 41 0

"O-

"ot

IN+

70 vt

O-3 b IN-

62 63

Fig. 1

  The first stage of operational amplifier 61 has a 63 are configured to reduce the impedance at the gain less than one thus it is an attenuating gain stage. inputs of amplification stage 67 to increase the pole Also, the output impedance provided by the first frequency of the first stage (thereby increasing stage to the inputs of amplification stage 67 (second bandwidth).
stage) is lowered due to resistors 64 and 65 which
further increases the bandwidth of the first stage. Transistors 62 and 63 (differential input transis- tor pair) have a common well or bulk region which Resistors 64 and 65 and load transistors 62 and reduces the area required for the transistors. The

(1 MOI"da. 1°C. 19% 88 March 1998

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MOTOROLA Technical Developments

common well is connected to node 68 which is at a substantially lower voltage than the power supply temlinal Vdd. Connecting the common well to node 68 reduces the body effect on transistors 62 and 63. This results in a smaller increase of the threshold voltages of transistors 62 and 63 such that a mini- mal device width increase is required to compensate for the body effect.

  Figure 2 is a schematic diagram of an opera- tional amplifier 71 that comprises a first stage 72 and a second stage 73. Both bipolar transistors and IGFETs are used in the design of operational ampli- tier 71. Operational amplifier 7 I is fully differential and includes an input IN+, an input IN-, an output OUT+, and an output OUT-.

i

I

I

I II

r ------- ------

i

I I I I

I

I I I I I I

Q "REF5

Fig. 2

  First stage 72 has wide bandwidth and a gain less than one. First stage 72 comprises transistors 74, 75, and 78, and resistors 76 and 77. Transistors 74 and 75 are formed in a common well or bulk region. The common we...