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EPS Inner Core Metal Layers and Cavity Plating Design for the Embedded Capacitor Substrate

IP.com Disclosure Number: IPCOM000008589D
Publication Date: 2002-Jun-25
Document File: 4 page(s) / 59K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for modifying the current EPS design by adding metal layers and cavity plating to the center core of the EPS structure. Benefits include reduced inductance of the electrical path from the capacitor to the die.

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EPS Inner Core Metal Layers and Cavity Plating Design for the Embedded Capacitor Substrate

Disclosed is a method for modifying the current EPS design by adding metal layers and cavity plating to the center core of the EPS structure. Benefits include reduced inductance of the electrical path from the capacitor to the die.

Background

Typical industry capacitors are multi-layer structures that connect internal capacitance planes to external contacts called electrodes. Capacitor electrodes are typically designed for surface mount assembly. In the standard EPS structure, the first metal layer of routing above the embedded capacitor is the outer copper layer of the internal thin core (see Figure 1b).

General Description

As power supplies are scaled, microprocessors demand more and more current in a shorter period of time (<1ns) to maintain performance. Sources of electrical current need to be close to the microprocessor for timing, and to reduce parasitic losses and noise associated with the path of delivery. The disclosed method uses embedded discrete chip capacitors in the packaging substrate supporting the silicon. Embedding capacitors directly below the silicon core in the substrate provides the most immediate path of current possible (other than on-die capacitance).

The disclosed method also redesigns the configuration of the electrode connection for any type capacitor. Figure 2a shows a top-down view of the circuit pattern. Figure 2b shows a cross section schematic of the el...