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Method for direct chip attachment using die back-side power delivery and through-silicon vias

IP.com Disclosure Number: IPCOM000008596D
Publication Date: 2002-Jun-25
Document File: 6 page(s) / 101K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for direct chip attachment (DCA) using die back-side power delivery and through-silicon vias. Benefits include the elimination of high-cost package substrates.

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Method for direct chip attachment using die back-side power delivery and through-silicon vias

Disclosed is a method for direct chip attachment (DCA) using die back-side power delivery and through-silicon vias. Benefits include the elimination of high-cost package substrates.

Background

              DCA is a way of packaging integrated circuits that eliminates the requirement for high-cost package substrates. However, DCA has not been feasible for microprocessors because the several thousand required connections are not compatible with the minimum pitch of the motherboard, given the amount of silicon surface space that is available. In future technology generations, the package substrate is expected to cost as much or more than the silicon chip, driving the requirement to find a substrate-free packaging technology.

              Conventionally, microprocessors are flip-chip bonded to a multilevel organic or ceramic substrate.  One example of such a package is a flip-chip pin grid array (FCPGA, see Figure 1). After attachment of an appropriate thermal solution, the package is typically attached to the motherboard by a socket. DCA is not possible for the high bump count and tight pitch of conventional CPU designs. The bump count is projected to be in excess of 5,000 in the next few years. To use DCA with such a large number of bumps on a PC or server motherboard poses major technical and cost challenges.

              For small devices on smaller high-density motherboards in devices like PDAs and cell phones, DCA is being used to eliminate the packaging of the die to save cost and reduce the package profile. Due to the low pin count on the die and the small high-density motherboard, the technology is already available for high volume manufacturing.

General description

              The disclosed method uses through-silicon vias to supply power delivery and ground return on the backside of the die for typical logic chip design (see Figure 2). This approach enables the reduction of the lead count by eliminating the power/ground bumps on the active side and limits the front-side bumps to I/O. As a result, the bump count is significantly reduced, and bump pitch can be enlarged to a ball grid array-like (BGA-like) pitch, enabling DCA.

              The key elements of the method include:

·        Power and ground vias are formed from the backside of the die and connect directly to metal levels on the frontside.

·        Power is delivered to the backside of the die by a power slug connecting onto these vias.

·        The requirement for power/ground routing on the active side of the die is reduced.

·        The requirement for power/ground bumps on the top metal level is eliminated.

·        The top metal layer is limited to I/O signal bumps and related power supply and ground return only.

·        Bump pitch can be increased to a BGA-compatible pitch, such as 0.65 mm.

·        Pins can be placed on the active side of the die to enable use of conventional socket technology without a package substrate.

Advantages

              The disclosed method provides advantages including the...