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Method for Increasing I/O Count on a Silicon Component Utilizing Advanced PCB and Assembly Technologies

IP.com Disclosure Number: IPCOM000008598D
Publication Date: 2002-Jun-25
Document File: 3 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for increasing the number of signal I/Os on a component package, while routing the increased I/Os in a four-layer motherboard. Benefits include the use of small, easily routable BGA packages.

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Method for Increasing I/O Count on a Silicon Component Utilizing Advanced PCB and Assembly Technologies

Disclosed is a method for increasing the number of signal I/Os on a component package, while routing the increased I/Os in a four-layer motherboard. Benefits include the use of small, easily routable BGA packages.

Background

The number of signal I/Os has increased with successive chipset generations. In addition, the interface speed for each generation has increased, requiring the allocation of more power delivery balls. More delivery balls ensure excellent return paths for signal balls, and provide robust power delivery for the silicon component. Currently, the only way to add I/Os to a component is by increasing the package size and/or the I/O depth on the package. This strategy increases the cost of the component, as well as the motherboard.

General Description

The disclosed method uses Via-in Pad (VIP) for BGA components, and 4mil line, 4mil space PCB routing technology. By combining these technologies, along with standard package and motherboard implementations, a very small, dense, and easily routable (on the motherboard) BGA package is produced. This method can be used for any BGA package development.

By mixing VIP land pads with standard BGA land pads of differing diameters, a complex and repeatable pattern of land pads is created which optimizes ball spacing, motherboard power delivery, and signal escape opportunities (breakout) from the BGA package (see Figure 1)...