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A MECHANISM FOR RECOVERY OF PRECALCULATED RELATIVE BRANCH TARGETS FROM ENDIAN MODE CHANGES

IP.com Disclosure Number: IPCOM000008620D
Original Publication Date: 1998-Mar-01
Included in the Prior Art Database: 2002-Jun-27
Document File: 3 page(s) / 156K

Publishing Venue

Motorola

Related People

Thomas A. Hoy: AUTHOR [+3]

Abstract

One of the time-critical tasks in the fetch unit of a high performance microprocessor is the calcula- tion of relative branch targets, This involves adding an offset specified in the instruction with the current fetch address. This relative branch target address is then used to fetch the next instruction, The branch target address calculation and the resultant cache access should make the desired instruction available as soon as possible. The target address calculation can be extremely critical given the constraints on the cache access.

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MOTOROLA Technical Developnwnts

A MECHANISM FOR RECOVERY OF PRECALCULATED RELATIVE BRANCH TARGETS FROM ENDIAN MODE CHANGES

by Thomas A. Hoy, David S. Levitan and Terence M. Potter

PROBLEM

  One of the time-critical tasks in the fetch unit of a high performance microprocessor is the calcula- tion of relative branch targets, This involves adding an offset specified in the instruction with the current fetch address. This relative branch target address is then used to fetch the next instruction, The branch target address calculation and the resultant cache access should make the desired instruction available as soon as possible. The target address calculation can be extremely critical given the constraints on the cache access.

  One way of relieving pressure on the branch target address calculation is to perform the add before the instruction is written into the cache. This effectively stores absolute branch targets in the cache instead of relative branch targets.

  At dispatch time, the branch target address is read from the cache and used to fetch the next instruction. If the endian mode has changed, the branch target address calculation is incorrect and will cause the wrong instruction to be fetched. One way of dealing with this problem is to flush the cache when the endian mode is changed. This alter- native is not acceptable because memory may be set up with both little-endian and big-endian pages, If the cache were flushed on every endian mode change, the effectiveness of this technique would be limited. Another alternative is to flush the cache when the first invalid branch target is identified. This has the benefit of simplicity but may be unnecessary if there are few relative branches. Yet another alter- native is to invalidate individual lines in the cache as an invalid branch target address calculation is identified. This has the benefit of removing only those lines that have the offending target address.

The third alternative is the method of choice. This invention provides an efficient method of

recovery when the endian mode at dispatch time is different than the endian mode used to precalculate relative branches stored in the cache.

SOLUTION

  The branch target address calculation can be overlapped with predecode generation so no extra cycles need to be allocated for the process. While moving the branch target address calculation before the cache alleviates a timing path in the dispatch cycle, it can create a large storage requirement on the cache. In order to save room in the cache, the old offset is overwritten by the new target address. Because the offset can be as few as I4 bits in the PowerPC instruction set, the entire target address cannot be stored in the same space as the original instruction in the cache. The solution is to overwrite the offset with the low-order bits of the target address calculation. The high-order bits are then taken care of during dispatch.

  One requirement is placed on the low-order address cal...