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Method for a bus controller with an FPGA-like circuit

IP.com Disclosure Number: IPCOM000008680D
Publication Date: 2002-Jul-02
Document File: 2 page(s) / 951K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a bus controller with a field programmable gate array (FPGA) like circuit. Benefits include improved functionality and improved performance.

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Method for a bus controller with an FPGA-like circuit

Disclosed is a method for a bus controller with a field programmable gate array (FPGA) like circuit. Benefits include improved functionality and improved performance.

Background

              Conventional bus controllers are typically hard-wired. Some of them are software-configurable but are limited to the predesigned modes. If a new mode or a new function that is not predesigned is required after the chip is made, the bus controller simply cannot handle it. A software workaround or some hardware glue logic must be implemented. An example is transmitting asynchronous transfer mode (ATM) cells on a 64-byte network. Each cell must be padded to make it at least 64 bytes long. A microengine or external glue logic must be added to do the padding because the bus controller is hard-wired.

Description

              The disclosed method is a bus controller with an FPGA-like circuit, enabling the addition of functions via programming (see Figure 1). The FPGA-like circuit has a specific gate-count and is programmable using any bus of the chip on which the bus controller resides.

              The steps for setting up the hardware-programmable bus controller include:

1.      Decide if the default bus controller is OK.
              a.           If yes, the bus controller bypasses the FPGA-like circuit.
              b.           If not, design new features targeting the FPGA like circuit of the bus controller.

2.      If the design fits into the FPGA-like circuit, generate the file for programming the FPGA-like circuit of the bus ...