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A Noise Resistant Wide Range Tuning Circuit for Single Supply Low-Voltage CMOS Phase-Locked Loops and Frequency Synthesizers

IP.com Disclosure Number: IPCOM000008682D
Publication Date: 2002-Jul-02
Document File: 5 page(s) / 7M

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a noise resistant, wide-range tuning for a low phase-noise, phase-locked loop or frequency synthesizer in a single supply, low-voltage CMOS process.

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A Noise Resistant Wide Range Tuning Circuit for Single Supply Low-Voltage CMOS Phase-Locked Loops and Frequency Synthesizers

Disclosed is a method for a noise resistant, wide-range tuning for a low phase-noise, phase-locked loop or frequency synthesizer in a single supply, low-voltage CMOS process.

Background

Currently, the stringent phase-noise specifications for most wireless standards dictates the use of LC oscillators. The tank capacitor is usually used as the tunable element. Because a monotonic C-V characteristic is used in closed loop operations, such as in a PLL or frequency synthesizer, the diode and MOSFET varactors suffer. The tuning range of these varactors is severely limited in a single supply, low-voltage process. Furthermore, to reduce coupling noise from the power supplies and substrate, a fully differential loop is preferred.

General Description

Main Concept

The disclosed method uses a MOS device which operates only in the inversion or the accumulation regions, and does not suffer from monotonicity in the C-V characteristic (see Figure 1). The regular NMOS and PMOS operate only in inversion. If the necessary processing steps are supported, the NMOS device (in the N-well) and the PMOS device (in the P-well) always operate in accumulation.

Circuit Description

The following describes the NMOS device maximum capacitance (Cox*W*L), and the minimum capacitance (Cov*W).

§         Maximum capacitance. If the gate voltage is higher than the bulk voltage (by the threshold voltage of the device), then an inversion layer forms at the Si surface below the gate. The inversion layer takes the voltage of the source/drain terminals and shields the bulk from the gate charge. The input capacitance is then Cox*W*L.

§         Minimum capacitance. If the source/drain voltage is higher than the gate voltage, then the inversion layer cannot form, even though the gate is a threshold voltage higher than the substrate. Therefore, the gate charge is supported by depleting the bulk, and the series capacitance asymptotically approaches 0. However, the overlap capacitance between the gate, source, a...