Browse Prior Art Database

Method for egress bus transfer optimization

IP.com Disclosure Number: IPCOM000008687D
Publication Date: 2002-Jul-02
Document File: 3 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for egress bus transfer optimization. Benefits include improved performance.

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Method for egress bus transfer optimization

Disclosed is a method for egress bus transfer optimization. Benefits include improved performance.

Background

              Small packet throughput is becoming a more important measure of an Ethernet controller’s performance. Voice-over-IP (VoIP) is an example of a conventional application that uses small packets and is very performance sensitive. Small packets are demanding on the system in many ways. There is a fixed overhead to process a packet regardless of the size. Small packets particularly tax the system bus (such as PCI). Each packet must be transferred separately across the bus. Each direct memory access (DMA) operation on the bus has associated startup latency. Given this burden, the system bus can often be a performance bottleneck for small packet performance.

              For small packets, each descriptor points to a separate packet in memory (see Figure 1). Each packet is read separately by the I/O controller then transmitted onto the network. Therefore, each packet is subject to the related DMA overhead, including latencies related to bus arbitration, addressing, cache flushes, memory contention, and other delays. These start up latencies are especially significant in bridges that are not close to memory.

General description

              The disclosed method enables multiple transmit packets to be transferred across the bus with a single DMA operation. This improves bus efficiency and throughput. It is especially helpful for small packet performance.

Advantages

              The disclosed method provides advantages including improved performance.

Detailed description

              The disclosed method has two parts. The first is a device driver that arranges multiple packets into contiguous memory. The second is an enhanced I/O controller that can transfer multiple packets (when arranged contiguously) with a single DMA operation.

              The device driver must be able to arrange packets contiguously in memory. However, this can only be done by copying the packets to be transferred into a buffer where it can be coalesced with other packets. This approach must be implemented in such a manner that the data copies do not become a performance bottleneck. An algorithm can detect when the percentage of packets below a specified size exceeds a threshold. Then, the algorithm copies packets below this threshold size to a coalesce buffer. For example, when 80% or more of the packets being sent are less than 180 bytes, then small packets are coalesced by copying.

              The second part of the disclosed method is an I/O controller that can burst read the now adjacent packets with a single DMA operation. Prior art I/O controllers cannot do this. The disclosed me...