Browse Prior Art Database

METHODOLOGY FOR LOW POWER STANDARD CELL DESIGNS

IP.com Disclosure Number: IPCOM000008694D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2002-Jul-03
Document File: 2 page(s) / 96K

Publishing Venue

Motorola

Related People

Daniel Cronin: AUTHOR [+2]

Abstract

The methodology described herein provides for a low power, high density standard cell library with which low power, highly dense, low frequency VLSI components may be quickly synthesized.

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MOTOROLA Technical Developments

METHODOLOGY FOR LOW POWER STANDARD CELL DESIGNS

by Daniel Cronin and Rick Fernandez

  The methodology described herein provides for a low power, high density standard cell library with which low power, highly dense, low frequency VLSI components may be quickly synthesized.

  This methodology focuses on techniques involving layout, device ratioing, and circuit topolo- gies to build dense, low power library cells which when taken as a whole form the standard cell library As a general rule, standard cell libraries are built for performance foremost, closely followed by density, and finally power. This approach to standard cell design prioritizes power foremost, followed by area, and then performance.

  In terms of layout, several guidelines are followed starting with the cell height selection. The height is driven by the minimum number of wiring channels required to rout the most complex cell in the library-typically the sequential cells. This results in dense cells and lends itself to small device widths (i.e. low gate capacitance). The small cell size has a direct impact on the final block size. The combined effect is smaller blocks and reduced gate and diffusion area which equates to lower power. A second emphasis within the layout is to minimize the cell's internal capacitance by reducing the Ml area, gate area and drain diffusion area of each individual cell. One such technique is to limit the amount of gate capacitance by pushing the active area towards the center of the image and growing towards the power rails as the device widths grow.

In addition, diffusion area is reduced as much as possible on the drain side of devices, legs of series devices are maintained at a minimum spacing, and minimum Ml is used for routing.

  The second area of emphasis is circuit topology. Cells are designed to minimize area and reduce input capacitance by "buffering" the outputs to achieve higher drive strengths. Traditionally high power tristate devices are replaced with lower power...