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METHOD AND APPARATUS FOR CLOCKING AND CONTROLLING A MULTISTAGE PIPELINED DIGITAL SYSTEM

IP.com Disclosure Number: IPCOM000008705D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2002-Jul-04
Document File: 4 page(s) / 195K

Publishing Venue

Motorola

Related People

Eran Pisek: AUTHOR [+3]

Abstract

Digital functions are usually implemented by means of a data path and a state machine which controls the data propagation through that data path.

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MOTOROLA Technical Developments

METHOD AND APPARATUS FOR CLOCKING AND CONTROLLING A MULTISTAGE PIPELINED DIGITAL SYSTEM

by Eran Pisek, Moshe Tarrab and Eytan Engel

INTRODUCTION

  Digital functions are usually implemented by means of a data path and a state machine which controls the data propagation through that data path.

  Regularly, complex digital functions use pipeline techniques to parallelize operations and speed up the total functionality. One of the require- ments of pipelined digital systems is the ability to start, stop and restart the pipeline operation, under certain conditions, without loss of data. An example of this situation is when no new data is available for processing, thus a "stop" signal is issued while pre- vious data is intended to propagate till the last stage of the pipeline before the machine actually stops, but each stage in the pipeline should preserve its status according to the last valid data without running on garbage data (See Figure 2). Major problems arise when such complex functions are controlled by a regular state machine (e.g. ring counter).

  This invention presents a new general method for implementing a state machine which controls the propagation of data into the pipelined data path according to a predefined pipelined structure, and

capable of halting and resuming operation dynami- cally under logical conditions.

PRIOR ART ARCHITECTURE

  A regular system based on pipelined architec- ture, uses a simple ring counter or state counter (see Figure I), It means that the system has only one set of clock generators which supply clocks to all the pipeline stages, In order to correctly deal with the pipeline edge problems (i.e. halting and restarting the pipe), the main system should do one of the following:

I. To detect the edges according to the start/stop signals and determine the stages in the pipeline that should be enabled or disabled accordingly. This solution results in increasing hardware complexity.

2. To ignore the edges and let all the stages continue their operation on garbage data so all valid data in the pipe are flushed. This solution may result in loss of data if the garbage data overrides the valid data (See example in Figure 2 for 4-stage pipelined system) or false controller inner counters counts.

stop

Start

PART 2

q - Delay Element

Fig. 1 Regular Ring Counter

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Technical Developments

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Fig. 2 Regular Pipeline

  Figure 2 shows a time propagation chart of a simplified 4-stage pipelined machine. Data is input to stage A, output of stage A is input to stage B, and so on until stage D. For simplicity it is assumed that each stage process its data in an equal amount of time and that the last valid data was input to the machine at step i, and the machine is requested to stop for intermediate data and status interrogat...