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INSULATING PASSIVATION AND ARC FILMS BY REACTIVE SPUTTERING OF M-Si TARGETS

IP.com Disclosure Number: IPCOM000008713D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2002-Jul-04
Document File: 5 page(s) / 213K

Publishing Venue

Motorola

Related People

Ramnath Venkatraman: AUTHOR [+3]

Abstract

Conventional metalization for integrated circuit (IC) devices involves the patterning of metallic thin films, typically Al, through deposition, lithography and reactive ion etching (RIE). Recently, the inlaid (or damascene) approach' is being increasingly identified as a technology for future generations of IC devices. In this approach, metal interconnects are patterned through a series of steps involving dielectric deposition, patterning of dielectric to define trenches (lines) and vias, metal till, and finally, by chemical mechanical polishing (CMP). The technology is referred to as 'dual inlaid' when trenches and via are both defined prior to metal fill.

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MOTOROLA Technical Dwelopmenis

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INSULATING PASSIVATION AND ARC FILMS BY REACTIVE SPUTTERING OF M-Si TARGETS

by Ramnath Venkatraman, Ajay Jain and Kevin Lucas

I. INTRODUCTION of dielectric gap fill steps and CMP,

  Conventional metalization for integrated circuit (IC) devices involves the patterning of metallic thin films, typically Al, through deposition, lithography and reactive ion etching (RIE). Recently, the inlaid (or damascene) approach' is being increasingly identified as a technology for future generations of IC devices. In this approach, metal interconnects are patterned through a series of steps involving dielectric deposition, patterning of dielectric to define trenches (lines) and vias, metal till, and finally, by chemical mechanical polishing (CMP). The technology is referred to as 'dual inlaid' when trenches and via are both defined prior to metal fill. The advantages of using this approach include:

a) simplification of process flow through elimination

b) elimination of a metal RIE process that is becoming increasing diffLxlt with shrinking line widths due to metal corrosion effects and residues that could cause electrical shorting,

c) significant advantages in lithography due to easier alignment between levels and patterning of thinner photoresist layers,

d) application of the technique to metals such as copper, which have been difficult to pattern through metal etching.

A schematic of a typical dual damascene structure is as shown in Figure I,

Metal fill (Cu, Al etc.)

Fig. 1 Schematic of a dual inlaid interconnect stmcture

  In order to define the stmctare shown in Figure I, etchstop) a dielectric layer, typically TEOS, an the dielectric stack typically consists of four layers: additional etchstop layer intended for delineating a passivation layer (which can also function as the trench pattern from the via pattern and finally,

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MOTOROLA Technical Developments

another layer of dielectric, typically TEOS. It is noted that the passivation and the etchstop layers can serve several purposes including:

a) barrier against diffusion of Cu between metal levels as well as into the transistors in the under- lying silicon, and,

b) anti-reflective coating (ARC) to minimize reflections from underlying layers during photo exposure in lithography.

  Furthermore, the top passivation layer can provide additional advantages in the integration of inlaid metalization such as acting a$ a CMP stop layer and as an etchstop layer. In addition to the above attributes, the ideal passivation layer also needs to be insulating and possess excellent adhesion to the underlying metal and the dielectric. The adhesion of the Cu to a number of commonly used dielectrics is known to be poor. In addition, Cu diffuses through a number of dielectrics during thermal annealing.

  We report here, a thin film material containing Ta, Si and N that is insulating and p...