Browse Prior Art Database

Method to Reduce Line Edge Roughness During Gate Etching

IP.com Disclosure Number: IPCOM000008739D
Original Publication Date: 2002-Jul-08
Included in the Prior Art Database: 2002-Jul-08
Document File: 5 page(s) / 64K

Publishing Venue

Motorola

Related People

Shahid Rauf: INVENTOR [+4]

Abstract

Line edge roughness at the transistor gate can appreciably deteriorate transistor electrical characteristics. This problem is expected to grow worse as transistor sizes decrease. A new method, reduces edge roughness on transistor gates, which can be used at different stages during the transistor gate definition process. In the proposed method, a fluorocarbon film is first deposited on the wafer surface in such a manner that the film is only present on horizontal surfaces and almost absent on vertical surfaces. Following it, ion assisted physical sputtering is used to remove rough bumps on the feature sidewalls. The fluorocarbon film deposited during the first step protects material at horizontal surfaces from energetic ions. The proposed technique can be used prior to photoresist trimming, after photoresist trimming, or after the gate formation process.

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Method to Reduce Line Edge Roughness During Gate Etching

Shahid Rauf, Jonathan Cobb, Phillip Stout, and Peter Ventzek

Abstract

Line edge roughness at the transistor gate can appreciably deteriorate transistor electrical characteristics.  This problem is expected to grow worse as transistor sizes decrease.  A new method, reduces edge roughness on transistor gates, which can be used at different stages during the transistor gate definition process.  In the proposed method, a fluorocarbon film is first deposited on the wafer surface in such a manner that the film is only present on horizontal surfaces and almost absent on vertical surfaces.  Following it, ion assisted physical sputtering is used to remove rough bumps on the feature sidewalls.  The fluorocarbon film deposited during the first step protects material at horizontal surfaces from energetic ions.  The proposed technique can be used prior to photoresist trimming, after photoresist trimming, or after the gate formation process.


Problem and its Solution

Experiments and simulations have demonstrated that line edge roughness at the transistor gate can deteriorate transistor electrical characteristics (Kaya et al., SISPAD 2001).  This problem is expected to get worse as the transistor size decreases, primarily because roughness becomes a larger fraction of the feature size.  Roughness is mainly transferred on the gate surface from the photoresist mask, where the photoresist surface becomes rough during the different lithography and etch steps due to the polymer nature of the photoresists.  Although effort is currently underway to reduce roughness on photoresist surfaces during the photoresist exposure and development, it will be useful to have processes that can smooth out the photoresist surface prior to or during the etch steps as well.  A smoother photoresist surface will lead to a smoother gate surface, with less line edge roughness and better electrical characteristics.

A new technique to reduce line edge roughness on photoresist and poly-Si gate surfaces is described.  This technique can be used prior to, during, or after the gate stack etch fabrication procedure to reduce line edge roughness on the final gate structure.

The basic idea that is being proposed consists of two steps, which have also been illustrated in Fig. 1:

  1. Coat a protective film on the wafer surface in such a manner that the film is present on horizontal surfaces and almost absent on vertical surfaces,
  2. Use ion-assisted physical sputtering to remove rough perturbations (bumps) on the feature sidewalls.

Fig. 1: A sketch of the primary idea proposed is this document.

The first step (protective film deposition) can be done in inductively coupled plasma of a fluorocarbon gas that mainly p...