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MODE- AND CYCLE-DEPENDENT TEST MODE TIMING FOR EMBEDDED MICROCONTROLLERS

IP.com Disclosure Number: IPCOM000008744D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2002-Jul-09
Document File: 3 page(s) / 170K

Publishing Venue

Motorola

Related People

Bill Getka: AUTHOR

Abstract

Small S-bit microcontrollers with embedded memory will typically have a number of pins dedi- cated to bringing the address and data bus in and out of the part for testability reasons. To minimize the number of pins required for this non-user function, it is desirable to multiplex as much information as possible onto each pin.

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MOTOROLA Technical Developments

MODE- AND CYCLE-DEPENDENT TEST MODE TIMING FOR EMBEDDED MICROCONTROLLERS

by Bill Getka

1 .O INTRODUCTION

  Small S-bit microcontrollers with embedded memory will typically have a number of pins dedi- cated to bringing the address and data bus in and out of the part for testability reasons. To minimize the number of pins required for this non-user function, it is desirable to multiplex as much information as possible onto each pin.

2.0 PROBLEM(S) TO BE SOLVED

  A high degree of multiplexing causes the timing on the test pins to become very critical. Traditionally, this timing is fixed to a particular format. For example, the timing on a given bus cycle might be made up of upper-order address followed by lower-order address followed by bi-directional data. The problem encountered with having a fixed format of this type is that the timing is not optimized for the bi-directional data. That is, the best time to drive data into the part is early in the cycle to ensure it arrives at its destination in time. On the contrary, the best time to have the part drive data out is late in the cycle so that the source has more time to get the data to the tester.

  Like many of today's microcontrollers, the HC08 microcontroller family has both a peripheral test mode (PTM) and CPU test mode (CTM). In the PTM, the address bus is driven by the tester while the CPU is kept inactive (slave mode). This test mode allows the tester to directly address any loca- tion in the memory map. In CTM, the CPU is the bus master just like in user mode, and opcodes and operands are fed by the tester to control the test flow. In CTM, the address bus is brought out of the

part so that the tester can verify the CPU's functiaa- ality. Therefore, the address bus is effectively a bi-directional bus just like the data bus is. The main difference is that the data bus can switch directions on a cycle-by-cycle basis whereas the address bus is a fixed direction for each mode.

  For both the address and the data buses, it would be most optimal if the tester timing format could be customized to the direction of the informa- tion. That is, if information is coming out of the part under test, it would be best if the timing were defined to bring it out late in the cycle whereas if the information is going into the part under test., it would be best to drive the part early in the cycle ((or even before the cycle itself).

3.0 SOLUTIONS TO THE PROBLEM(S)

  A viable solution to this timing problem is to not require the timing format for the test bus to remain constant between test modes (PTM and CTM) or even test cycles (read and write). Since the tester can deterministically predict ahead of time what type of cycle it is going to be, it can switch its timing to accommodate this variability. This concept of decoding the type of test mode transfer being done (either into the part or out of the part) on a mode and cycle-by-cycle basis to determine the type of timi...