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A Power-Saving Mechanism for a DMA Address Bus

IP.com Disclosure Number: IPCOM000008766D
Original Publication Date: 2002-Jul-10
Included in the Prior Art Database: 2002-Jul-10
Document File: 5 page(s) / 86K

Publishing Venue

Motorola

Related People

Eytan Hartung: INVENTOR [+2]

Abstract

A typical DMA controller operates under the control of a microprocessor. The microprocessor instructs the DMA controller to transfer a block of data from consecutive locations in memory to consecutive locations in another region of the memory space. The microprocessor provides the DMA controller the source and destination starting addresses and the number of words to be transferred. The DMA controller maintains the address pointers as well as a word counter. Existing DMA controllers begin at the provided starting address and access the memory locations in numerical order. This article describes a mechanism that saves up to 50% of the address current-drain by utilizing a dynamically adjustable counter that for an address bus width of m will address the n lowest significant bits in Gray code sequence while counting the upper m-n bits in binary code. The dynamically adjustable selection of n maximizes the benefit for any buffer size and location. Also - it transfers the data in a Gray code sequence, but preserves the original data order once it is stored in memory, a requirement for DMA transfers. Therefore This mechanism is not limited in term of subsequent accesses to the stored data must be transferred as entire block, and thereby not limiting the application to fixed size blocks.

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       A Power-Saving Mechanism for a DMA Address Bus

Eytan Hartung

Vasan Venkataraman

Abstract

 A typical DMA controller operates under the control of a microprocessor. The microprocessor instructs the DMA controller to transfer a block of data from consecutive locations in memory to consecutive locations in another region of the memory space. The microprocessor provides the DMA controller the source and destination starting addresses and the number of words to be transferred. The DMA controller maintains the address pointers as well as a word counter. Exist­ing DMA controllers begin at the provided starting address and access the memory locations in numerical order.

 This article describes a mechanism that saves up to 50% of the address current-drain by utilizing a dynamically adjustable counter that for an address bus width of m will address the n lowest significant bits in Gray code sequence while counting the upper m-n bits in binary code.

The dynamically adjustable selection of n maximizes the benefit for any buffer size and location. Also - it transfers the data in a Gray code sequence, but preserves the original data order once it is stored in memory, a requirement for DMA transfers. Therefore – This mechanism is not limited in term of subsequent accesses to the stored data must be transferred as entire block, and thereby – not limiting the application to fixed size blocks.

Body

In a standard numerical counting sequence, the individual bits of the binary address bus undergo many transitions during the course of a block transfer. For example, when transferring 8 words beginning at address “xxxx_x000”, the following transitions occur:

xxxx_x000

xxxx_x001 - 1 bit-transition from the previous address

xxxx_x010 - 2 bit-transitions from the previous address

xxxx_x011 - 1 bit-transition from the previous address

xxxx_x100 - 3 bit-transitions from the previous address

xxxx_x101 - 1 bit-transition from the previous address

xxxx_x110 - 2 bit-transitions from the previous address

xxxx_x111 - 1 bit-transition from the previous address

=> 11 bit-transitions to complete the 8-word transfer

This method proposes the use of a Gray-code counting sequence to reduce the total number of bit-transitions on the address bus, providing the benefit of reduced switching noise and reduced switching current. This method is applicable in the typical DMA transfer process where the order in which the data words are transferred is not important. This mechanism may be imple­mented in an otherwise binary counting system without affecting system performance or requir­ing specially compiled system code.

Using the example above, the same 8 memory locations would be accessed in the following order:

xxxx_x000

xxxx_x001 - 1 bit-transition from the previous address

xxxx_x011 - 1 bit-transition from the previous address

xxxx_x010 - 1 bit-transition from the previous address

xxxx_x110 - 1 bit-transition from the previous address

xxxx_x111 - 1 bit-transition from the previous address

xxx...