Browse Prior Art Database

TESTING EMBEDDED ROM USING SPECIAL MODEL WITH ATPG TOOLSET

IP.com Disclosure Number: IPCOM000008770D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2002-Jul-11
Document File: 2 page(s) / 106K

Publishing Venue

Motorola

Related People

Benoit Bailliet: AUTHOR [+2]

Abstract

Testing the content of an Embedded ROM is a common problem in a design: it usually requires additional hardware to have access to the addressesidatas and human effort to develop a design-specific software that will generate a pattern, taking as input the values of the ROM.

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MOTOROLA Technical Development.r

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TESTING EMBEDDED ROM USING SPECIAL MODEL WITH ATPG TOOLSET

by Benoit Bailliet and Serge Alin

1 DEFINITION OF THE PROBLEM

  Testing the content of an Embedded ROM is a common problem in a design: it usually requires additional hardware to have access to the addressesidatas and human effort to develop a design-specific software that will generate a pattern, taking as input the values of the ROM.

  If an ATPG tool is used to test the block con- taining the embedded ROM, the ROM is modeled as a "black-box", model provided by the tool vendor, taking as input the content of the ROM. The functional model of this "black-box" will be, for a given address and clock valid, a given data value (address=006a and clock=1 => data=a5e4).

  But these vendor-provided models don't allow us to put faults inside the ROM itself. The ATPG tool will use the functional model of the ROM to test the surrounding logic (therefore it will test part of the ROM), but we cannot constrain the tool to

test all the locations of the ROM, i.e. to get 100% Test Coverage of the ROM.

2 INVENTION

  We have created a special model for the ROM (schematic based but can also be high level lan- guage based model) that allow us to put faults inside the memory and test 100% of those faults using the ATPG tool. In our case, we adapted this solution to the Mentor FIexTestiFastScan tools but it can be used with any other tools.

  This model contains an address decoder, a clock and a "mm content" block (representation of the memory points). For a MxN ROM (M number of lines or addresses, N size of the output data bus), the address decoder generates M read enable signals (one for each lines). Each enable signal is gated with the clock to respect the functionality: the M resulting signals are inputs for the rom-content block, read(j).

( ( I

for i:= 0 (0 Ei- I ICUWJ,

for i:= 0 to M-l

nad(M- I :O)

ROM content description

r: Mot"r",a. Inc. ,998 198 June I998

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MOTOROLA Techtbd Developments

  The content of this block is MxN tristate buffers (tbuf): the input of every tbuf can be considered as a memory bit (rom_content(i+Nxj)), the enable line is connected to one of the read(j) signal, the output is connected to data(i) net.

  A NET propert...