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A Method for Barrier Seed Integration for ULSI Copper Metallization

IP.com Disclosure Number: IPCOM000008807D
Original Publication Date: 2002-Jul-15
Included in the Prior Art Database: 2002-Jul-15
Document File: 5 page(s) / 532K

Publishing Venue

Motorola

Related People

Rajesh A. Rao: INVENTOR [+3]

Abstract

A method for barrier-seed integration for the fabrication of Cu interconnect lines in high aspect ratio trenches and vias in the bank end of the line (BEOL) of typical IC processing is described. Conformal coverage of the thin barrier layer and Cu seed in such deep trenches and vias continues to be a challenge. The method described consists of using Atomic Layer Chemical Vapor Deposition (ALCVD) to deposit the barrier metal (typically Ta or TaN or a bilayer Ta/TaN) and a very thin layer of a catalyst metal such as Pt, Sn, Pd or Cu. This is followed with an electroless plating step during which the catalyst metal deposited in the previous step serves as an activation layer for electroless deposition of the Cu seed. Once a sufficiently thick Cu seed is deposited, the vias and trenches are filled with Cu in an electroplating process. This integration scheme eliminates the need for a physical vapor deposition step, which is the primary cause for step coverage related failures in BEOL interconnects.

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A Method for Barrier – Seed Integration for ULSI Copper Metallization

Rajesh A. Rao, Muralidhar Ramachandran, and Bich-Yen Nguyen

A method for barrier-seed integration for the fabrication of Cu interconnect lines in high aspect ratio trenches and vias in the bank end of the line (BEOL) of typical IC processing is described.  Conformal coverage of the thin barrier layer and Cu seed in such deep trenches and vias continues to be a challenge.  The method described consists of using Atomic Layer Chemical Vapor Deposition (ALCVD) to deposit the barrier metal (typically Ta or TaN or a bilayer Ta/TaN) and a very thin layer of a catalyst metal such as Pt, Sn, Pd or Cu.  This is followed with an electroless plating step during which the catalyst metal deposited in the previous step serves as an activation layer for electroless deposition of the Cu seed.  Once a sufficiently thick Cu seed is deposited, the vias and trenches are filled with Cu in an electroplating process.  This integration scheme eliminates the need for a physical vapor deposition step, which is the primary cause for step coverage related failures in BEOL interconnects.

The fabrication of ultra large scale integrated (ULSI) devices requires integrating a high density of Cu interconnects in the back end of the line (BEOL).  State-of-the-art Complementary Metal Oxide Semiconductor (CMOS) process integrated circuits contain many levels of metallization which are separated by interlayer dielectrics.  The process flow calls for forming contact vias the dielectric material to make electrical contact to the underlying metal level.  A barrier metal such as Ta or TaN and a PVD Cu seed is conformally deposited in these vias.  This is followed with the Cu electroplating, using the PVD Cu as a seed, to fill the vias.  The very high aspect ratio of these trenches and features makes it challenging to obtain a conformal barrier and seed deposition using PVD techniques.  For instance, in a 0.18 micron technology backend, the deposition of 400A of barrier metal (Ta) and 1000A of Cu seed layer by PVD leads to asymmetric deposition with more material deposited on the top and negligible deposition in the bottom corners and sidewalls of the vias, as shown in fig. 1.  Achieving conformal step coverage and void free fill with the subsequent copper seed and fill depositions is even more challenging in the dual damascene integration, which has larger aspect ratios.  The thickness of the PVD seed layer required for electroplating looms as a threat to continued scaling in the back end.  A discontinuous seed may result in poor trench and via fill leading to yield impacting voids in the interconnect structure.  To improve the barrier layer conformality, many new deposition techniques have been used.  Most recently, ionized metal plasma (IMP) PVD[1] and long throw sputter deposition[2] for the barrier and Cu seed has been used, but other techniques such as electroless plating and atomic layer chemical vapor deposition (ALCVD) will...