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DGO Formation by Lateral Oxidation

IP.com Disclosure Number: IPCOM000008808D
Original Publication Date: 2002-Jul-15
Included in the Prior Art Database: 2002-Jul-15
Document File: 4 page(s) / 124K

Publishing Venue

Motorola

Related People

Christopher C. Hobbs: INVENTOR

Abstract

Silicon dioxide (SiO2) has been the MOSFET gate dielectric of choice over other dielectrics because of its physical and electrical properties. However, as MOSFET dimensions are scaled, the gate leakage current becomes unacceptably high when the SiO2 is scaled to a thickness range where direct tunneling is the primary conduction mechanism. To achieve a lower leakage current at the same equivalent oxide thickness (EOT), the SiO2 can be replaced with a thicker dielectric that has a higher permittivity. Metal oxide insulators such as zirconium dioxide (ZrO2) and hafnium dioxide (HfO2) are examples of two dielectrics with permittivities higher than SiO2. To form a metal oxide with an extremely low electrical oxide thickness (tox), it is extremely important to control the surface preparation. The ability to scale down the thickness of a metal oxide will be limited by the quality and thickness of any surface oxide or pretreatment. Thus it is desirable to remove the native oxide on the surface prior to formation of the metal oxide gate dielectric. Two methods for removing a native oxide are HF cleaning and hydrogen baking at elevated temperatures. On a chip, it is desirable to have MOSFETs with different gate dielectric thickness to address the needs for high and low voltage operation. A thin gate dielectric is used for the high performance device that is operated using low voltages whereas a thicker gate dielectric is used for MOSFETs that are operated using high voltages. The presence of two such different dielectrics is referred to as a Dual Gate Oxide (DGO).

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DGO Formation by Lateral Oxidation

Christopher C. Hobbs

Abstract

Silicon dioxide (SiO2) has been the MOSFET gate dielectric of choice over other dielectrics because of its physical and electrical properties. However, as MOSFET dimensions are scaled, the gate leakage current becomes unacceptably high when the SiO2 is scaled to a thickness range where direct tunneling is the primary conduction mechanism. To achieve a lower leakage current at the same equivalent oxide thickness (EOT), the SiO2 can be replaced with a thicker dielectric that has a higher permittivity. Metal oxide insulators such as zirconium dioxide (ZrO2) and hafnium dioxide (HfO2) are examples of two dielectrics with permittivities higher than SiO2.

To form a metal oxide with an extremely low electrical oxide thickness (tox), it is extremely important to control the surface preparation. The ability to scale down the thickness of a metal oxide will be limited by the quality and thickness of any surface oxide or pretreatment. Thus it is desirable to remove the native oxide on the surface prior to formation of the metal oxide gate dielectric. Two methods for removing a native oxide are HF cleaning and hydrogen baking at elevated temperatures.

On a chip, it is desirable to have MOSFETs with different gate dielectric thickness’ to address the needs for high and low voltage operation. A thin gate dielectric is used for the high performance device that is operated using low voltages whereas a thicker gate dielectric is used for MOSFETs that are operated using high voltages. The presence of two such different dielectrics is referred to as a Dual Gate Oxide (DGO).

Unfortunately, a HF last clean or hydrogen bake cannot be used in a conventional DGO process because it will degrade the quality the thicker SiO2 gate dielectric. A different integration is required to implement a thin gate dielectric with an HF last clean. This integration proposes using a lateral oxidation process to form a DGO after the gate electrode is in place. It consists of (a) forming a polySi (or SiGe) gate on top of a metal oxide gate dielectric, (b) masking of certain devices with a oxygen barrier, (c) performing an oxidation that will grow interfacial oxide layers above and below the metal oxide gate dielectric and (d) removing the remaining portion of the oxygen barrier. By forming the thick oxide stack after the thin metal oxide, this enables the use of either an HF last clean or hydrogen bake prior to the formation of the thin metal oxide device.

DGO Integration Process

The DGO Lateral Oxidation integration process begins by using a conventional CMOS integration process. The conventional process sequence is followed up to the formation of the first gate dielectric. It is at this point in the flow that the HF-last clean or hydrogen bake is performed and a thin metal oxide layer is formed. Metal oxides that can be used include but are not limited to HfO2, ZrO2, Hf-silicate (HfSiXOY), Zr-silicate (ZrSiXOY), HF-alum...