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METHOD OF IMPROVING CONTACT ETCH MARGIN BY REDUCING OXIDE THICKNESS IN N+ DOPED CONTACTS USING N+ IMPLANT EXCLUSION MASK

IP.com Disclosure Number: IPCOM000008831D
Original Publication Date: 1998-Sep-01
Included in the Prior Art Database: 2002-Jul-17
Document File: 2 page(s) / 103K

Publishing Venue

Motorola

Related People

Kevin Cox: AUTHOR [+3]

Abstract

A technique for defining an implant mask which can improve process margin for the poly 2 to N+ con- tact etch for CMOS or BiCMOS processes that com- bine post-N+ implant oxidizing anneals with self- aligned poly 2 to N+ contacts and silicon dioxide gate capping layers. By careful exclusion of the N+ implant from the poly2 to N+ contact area the thick- ness of thermal oxide in the N+ regions is reduced by elimination of dopant enhanced oxidation in those areas. regions is as much as 5 times lower than the etch rate of the gate cap oxide. Minimizing the oxide thickness in N+ to poly 2 contact regions adds process controlla- bility.

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MOTOROLA Technical Developments

METHOD OF IMPROVING CONTACT ETCH MARGIN BY REDUCING OXIDE THICKNESS IN N+ DOPED CONTACTS USING N+ IMPLANT

EXCLUSION MASK

by Kevin Cox, Craig Gunderson, Norm Herr

ABSTRACT

  A technique for defining an implant mask which can improve process margin for the poly 2 to N+ con- tact etch for CMOS or BiCMOS processes that com- bine post-N+ implant oxidizing anneals with self- aligned poly 2 to N+ contacts and silicon dioxide gate capping layers. By careful exclusion of the N+ implant from the poly2 to N+ contact area the thick- ness of thermal oxide in the N+ regions is reduced by elimination of dopant enhanced oxidation in those areas.

regions is as much as 5 times lower than the etch rate of the gate cap oxide. Minimizing the oxide thickness in N+ to poly 2 contact regions adds process controlla- bility.

BACKGROUND AND PROBLEM

   During CMOS wafer processing it is often neces- sary to use oxidizing anneals after N+ source drain implants to anneal damage or provide for full activa- tion and redistribution of dopants. During the oxidiz- ing anneals the oxide growth proceeds as much as 10 times much faster in the heavily doped N+ regions than in all other areas of the wafer due to dopant enhanced oxidation effects. The presence of thick thermal oxides over N+ regions can cause process control issues dur- ing subsequent oxide etches of the N+ source drain region to form N+ contacts. A specific example is when a "self-aligned" contact with oxide gate cap is used. In this process it is desirable to minimize the amount of oxide removed during the self-aligned con- tact etch so as to conserve poly 1 to poly 2 isolation but it is also a requirement that sufficient oxide is etched to insure that the N+ regions are completely clear of oxide. The process control challenge is exacerbated by the...