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Enhancing SPI protocol to enable Asynchronous Master or Slave transfer request.

IP.com Disclosure Number: IPCOM000008835D
Original Publication Date: 2002-Jul-17
Included in the Prior Art Database: 2002-Jul-17
Document File: 3 page(s) / 42K

Publishing Venue

Motorola

Related People

Mark Austin Lee: INVENTOR

Abstract

The SPI interface Synchronous Peripheral Interface is a high speed, low latency, low pin count, used for communicating from microprocessors to simple peripheral components in embedded systems. The HW simplicity of the SPI interface has led to its successful deployment. SPI is based on a simple Master/Slave relationship and defined frame structures that does not adequately address Network layer where for the Slave device to establish and terminate network communications. The additional functions are needed to facilitate products where slave devices provide a higher level of functionally. These functions can simply be implemented with low SW overhead utilizing the CSPI HW on the Motorola DragonBall MX1 processor.

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Enhancing SPI protocol to enable Asynchronous Master or Slave transfer request.

Author          Mark Austin Lee

Abstract:

The SPI interface “Synchronous Peripheral Interface” is a high speed, low latency, low pin count, used for communicating from microprocessors to simple peripheral components in embedded systems.  The HW simplicity of the SPI interface has led to its successful deployment.  SPI is based on a simple Master/Slave relationship and defined frame structures that does not adequately address Network layer where for the Slave device to establish and terminate network communications.  The additional functions are needed to facilitate products where slave devices provide a higher level of functionally.  These functions can simply be implemented with low SW overhead utilizing the CSPI HW on the Motorola DragonBall MX1 processor.

Body

The Serial Peripheral Interface (SPI) is a simple HW interface primarily used to transfer data to and from IC’s in embedded systems.  The basic SPI is a full duplex, four wire synchronous serial interface based on a Master/Slave relationship FIGURE 1.  The SPI signals are serial clock SCK, slave select /SS, Master Out Slave In MOSI, and Master In Slave Out MISO.  During a SPI transfer, data is simultaneously transmitted and received, data bits are shifted out/in based on SCK rising (or falling) edges FIGURE 2.

FIGURE 1:  four wire master slave hook up

Figure 2: timing diagram of typical SPI

All SPI communications are initiated by the SPI Master and thus...