Browse Prior Art Database

Parity Implementation for Dual-Flash EEPROM Microcontroller

IP.com Disclosure Number: IPCOM000008837D
Original Publication Date: 2002-Jul-17
Included in the Prior Art Database: 2002-Jul-17
Document File: 2 page(s) / 14K

Publishing Venue

Motorola

Related People

Mark Weidner: INVENTOR [+3]

Abstract

Parity checking is required on a microcontroller with a large embedded flash eeprom memory unit. Since the data in a re-writable memory unit, the parity information must also be in a re-writable unit. This invention is intended to provide the most area and test time efficient implementation for the data and parity, given the large flash eeprom memory required.

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Advanced Vehicle Systems Division

Parity Implementation for Dual-Flash EEPROM Microcontroller

Mark Weidner, Jason Perez, Joe Jelemensky

Abstract

Parity checking is required on a microcontroller with a large embedded flash eeprom memory unit. Since the data in a re-writable memory unit, the parity in- formation must also be in a re-writable unit. This invention is intended to pro- vide the most area and test time efficient implementation for the data and parity, given the large flash eeprom memory required.

A state-of-the-art microcontroller is being designed with a large amount of flash eeprom. The size of the memory required and the performance required is stretching the capability of the embedded flash eeprom memory technology. Due to this, the memory must be composed of two memory units. The micro- controller application requires parity for these units also.

The overhead in decoders, sense amps, and analog control circuits in a flash memory is high. Each flash memory unit also has overhead in test time. Thus, it is desired to implement the main memory and parity memory with the least number of memory units, to get the most area efficient and test-time efficient design.

To meet this criteria, the parity information is embedded in the two main flash eeprom memory units with the data. The parity information for memory unit 'A' is placed in memory unit 'B', and vice-versa. See attached Figure 1. The two memory units are read in parallel to get the data and parity...