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Method to use unit distance consecutive addresses for FIFOs with standard memories

IP.com Disclosure Number: IPCOM000008843D
Publication Date: 2002-Jul-17
Document File: 2 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use unit distance consecutive addresses for first-in, first-out registers (FIFOs) with standard memories. Benefits include improved performance and improved power consumption.

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Method to use unit distance consecutive addresses for FIFOs with standard memories

Disclosed is a method to use unit distance consecutive addresses for first-in, first-out registers (FIFOs) with standard memories. Benefits include improved performance and improved power consumption.

Background

              FIFOs typically use binary counters for their read and write pointers. When the count increases, many bits in the pointer switch with different propagation delays. As these bits switch, the FIFO memory that is addressed by the read counter consumes power as various intermediate addresses are selected and read out from the memory.

              A unit distance counter switches only 1 bit from one count value to the next consecutive count value. Unit distance counters can be used on a standard memory that is binary addressable as long as the sequence of the read pointer matches the sequence of the write pointer. The implementation of a unit distance counter typically takes less logic and runs faster than a binary counter.

Description

              The disclosed method uses unit distance counters for the read and write pointers. As the unit distance counter increases, only 1 bit switches. The next element from the FIFO’s memory is accessed without intermediate accesses (see Figure 1). This approach saves memory access power.

              After the chip resets, both the read pointer and the write pointer are initialized to the same value. Because both pointers go through the same unit distance code sequence, the order in which da...