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Architecture for a Low Power Butterfly Unit for Viterbi and BCJR Decoders

IP.com Disclosure Number: IPCOM000008852D
Publication Date: 2002-Jul-17
Document File: 4 page(s) / 132K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a Viterbi decoder with a butterfly base of four adders/comparators. Benefits include a 20% reduction in power and a 20% reduction in area.

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Architecture for a Low Power Butterfly Unit for Viterbi and BCJR Decoders

Disclosed is a method that uses a Viterbi decoder with a butterfly base of four adders/comparators. Benefits include a 20% reduction in power and a 20% reduction in area.

Background

Originally, a butterfly module calculated the value of two new state metrics. The calculation was done recursively from previous state metrics and the current branch metrics (BMn). Because the number of branch metrics is typically much lower than the number of states, all possible branch metrics were calculated and the relevant value was selected using a multiplexer. The original implementation of the butterfly is described by Equation 1 and

Figure 1. The outputs of the butterfly are the new state metrics and the selection bits (stored in the backtrace).

Currently, a new method has been proposed which reduces the need from six adder/comparators to five. The method is based on Equation 2 and Equation 3.

The implementation requires 5 adder/comparators and multiplexing of the branch metrics. In total this method requires a multiplexer 21/R->1 for 4 binary words (each word is typically 5-8 bits width).

General Description

The disclosed method has two parts; each one can be used independently of the other. The first part changes the multiplexer type from 21/R ->1 to 21/R-1 ->1 (e.g. from 8->1 to 4->1). The second part reduces the number of adder/comparators by one.

The first part changes the butterfly interface in Figure 1 to th...