Browse Prior Art Database

Method for die-package integration to support ultralow-K integration

IP.com Disclosure Number: IPCOM000008886D
Publication Date: 2002-Jul-19
Document File: 5 page(s) / 83K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for die-package integration to support ultralow-K integration. Benefits include improved reliability, improved support for future processes, and improved throughput.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Method for die-package integration to support ultralow-K integration

Disclosed is a method for die-package integration to support ultralow-K integration. Benefits include improved reliability, improved support for future processes, and improved throughput.

Background

              Conventionally, the epoxy process makes use of capillary flow to dispense underfill material between the die and substrate. This process places severe limitations on the minimum bump pitch and the minimum gap height between the die and the substrate, which are essential for future generations of microprocessors. Furthermore, the capillary underfill process limits the material set, reduces the process window, and is prone to voiding issues. In addition, the process limits equipment throughput and is expensive.

              Conventionally, Cu bumps are electroplated on the die while solder is screen printed on the substrates. Modeling and experimental data have shown that Cu bumps on the die significantly increase the stress on the dielectric material in the die, leading to cracking and delamination.

              Conventionally, the underfill process issues are solved by extensive material and process optimization. Interlayer dielectric (ILD) stress is being addressed by optimizing the dielectric material properties, adhesion, and all process steps, including fabrication and assembly.

              The conventional method includes the following assembly steps (see Figures 1 and 2):

1.      Solder is screen printed on package with solder resist mask.

2.      Cu bumps are electroplated on Si using a thick photoresist to define the bumps.

3.      Underfill is dispensed unit-by-unit and cured afterwards after chip joint process. Underfill voids are related to the material flow property and die bump pattern.

General description

      The disclosed method is die-package integration to support ultralow-K integration. A spin-on underfill precursor on the Si wafer and the package panel serves as resist for Cu bump plating on the package and solder plating on the wafer. The underfill is fully cured at the chip joint process.  

              The key elements of the method include:

·        Underfill material is a part of the substrate and the die.

·        Bump pitch, diameter, and bump height are tailored to reduce stress on the dielectric in the die.

·        Cu bump is plated on the package to reduce ILD stress on the die, which is crucial for low-K and ultralow-K integration in future generations of semiconductor chips.

·        Underfill is fully cured during the chip joint process.

 


Advantages

              The disclosed method provides advantages, including:

·        Improved reliability due to the prevention of underfill voiding issues and eliminating stringent limitations on bump pitch, gap height, underfill materials

·        Improved reliability due to the optimization of the bump height and diameter to reduce stress on low-K dielectric layers without any capillary flow-related limitati...