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Method for RAM allocation and performance improvement of high-performance packet relay in a switch with configurable link widths

IP.com Disclosure Number: IPCOM000008927D
Publication Date: 2002-Jul-24
Document File: 5 page(s) / 109K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for random access memory (RAM) allocation and performance improvement for high-performance packet relay in a switch with configurable link widths and virtual lanes. Benefits include improved performance.

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Method for RAM allocation and performance improvement of high-performance packet relay in a switch with configurable link widths

Disclosed is a method for random access memory (RAM) allocation and performance improvement for high-performance packet relay in a switch with configurable link widths and virtual lanes. Benefits include improved performance.

Background

              Conventionally, a lx-wide packet on a 4x-wide crossbar relays at one-fourth the available bandwidth by transferring, in time-slice fashion, one word every fourth timeslot.

              Examples assume that all VLs have packets accumulated to be relayed.

              Speed up is the ratio of the packet relay rate to the input link rate per quad port.

              Conventional implementations are either expensive or too sluggish.

General description

              The disclosed method allocates RAM and speeds up high-performance packet relay in a switch with configurable link widths. Receive and transmit RAM provides higher bandwidth across VLs when they have packets accumulated due to downstream credits being unavailable. In addition, the RAM provides paths through the crossbar for 1x packets. Accumulated words can be drained at four times the link rate.

Advantages

              The disclosed method provides advantages, including:

•             Improved performance due to higher bandwidth

•             Improved performance due to the availability of more VLs to send packets on the output link

•             Improved performance due to the availability of more receive RAM to handle more packets

•             Improved cost effectiveness

Detailed description

              The disclosed method pertains to the architecture of a switch with four ports (quad-ports) that are configurable as four lx links or one 4x link. The switch, which incorporates both receive and transmit RAMs, supports up to two VLs for lx configured ports and up to eight VLs for 4x configured ports. The disclosed method provides higher bandwidth across VLs when they have packets accumulated due to downstream credits being unavailable. The packet accumulation worsens under bursty traffic. The disclosed method attains an attractive cost-performance solution by allocating RAMs among ports and VLs.

              One implementation of the method is to designate one transmit and one receive RAM per quad-­port (see Figure 1). Each RAM would have a single crossbar connection with a bandwidth of one 4x link. The width of each input link is 16 bits, and the width of crossbar is 64 bits. In this case, all eight VLs of a 4x port (quad-port) would share a receive/transmit RAM. In the case where the quad-port is configured for lx operation, both VLs of each of the four lx ports would share a receive/transmit RAM. In the former case, it is possible to relay a packet from one out of eight VLs. In the latter, it is possible to relay one out of two VLs from one out of four ports. The small crossbar and the modest use of RAM keep the cost low. This implementation permits only one VL per quad port, to relay packet on the crossbar, when there can be multiple VLs with packets availab...