Browse Prior Art Database

Method for a scratch-ring infrastructure

IP.com Disclosure Number: IPCOM000008930D
Publication Date: 2002-Jul-24

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for scratch-ring infrastructure. Benefits include improved performance, improved functionality, and improved design flexibility.

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Method for a scratch-ring infrastructure

Disclosed is a method for scratch-ring infrastructure. Benefits include improved performance, improved functionality, and improved design flexibility.

Background

              A network processor system with a 6.26-GBps input/output (I/O) bus includes seven RISC processors, six microengines (MEs) and an embedded microprocessor. The embedded microprocessor  handles the control-plane traffic and  six microengines work together to handle data-plane traffic. During packet processing activity, microengines pass packet context information from one microengine to another using scratch ring infrastructure. The main function of the microengines is to process packets at the fastest possible time. Because the performance of the entire system depends on the ring infrastructure, ring produce and consume operations should be executed at a very fast rate.

              Conventional designs use sram_read_lock and sram_write_unlock instructions with rings. These SRAM and SDRAM operations are much slower than scratch operations. All conventional SRAM and SDRAM references go to an external device that is outside the embedded network processor.

              The conventional size of a ring metadata structure is 4 long words (16 bytes).

              The ring consume operation in conventional designs always consumes only one packet at a time. Three memory accesses are required:

1.      Scratch read, to get ring metadata

2.      SRAM read, to get ring data

3.      Scratch write, to put updated metadata.

General description

              The disclosed method is a scratch ring infrastructure. The main components of the method include ring produce and consume operations that are used to pass packet context information from one microengine to another in a network processor system with a 6.26-GBps I/O bus.

              The method uses scratch atomic instructions to operate on rings. Because scratch memory is internal to the processor, these operations are much faster than with the conventional method.

              The disclosed design uses a single long word (4 bytes) because all ring metadata are packed into a 32 bit scratch location and memory is not wasted. Multiple functions can be performed in a single scratch atomic instruction.

              The disclose method consumes next-packet context information along with the current packet if the ring size is greater than one. Using this technique, the number of memory I/O operations are significantly reduced.

Advantages

              The disclosed method provides advantages, including:

·        Improved performance due to the use of scratch memory that is internal to the processor

·        Improved performance due to the execution of multiple functions in a single scratch atomic instruction

·        Improved performance due to the reduced number of memory I/O operations because next-packet context information is  consumed along with the current packet

·        Improved performance due to the use of the read-modify-write technique of scratch atomic operations

·        Improved performance due to specialized data structures for ring meta data and ring dat...