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Method for an electro-migration optimized ratio-logic device layout pattern

IP.com Disclosure Number: IPCOM000008931D
Publication Date: 2002-Jul-24
Document File: 5 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an electro-migration optimized ratio-logic device layout pattern. Benefits include improved performance.

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Method for an electro-migration optimized ratio-logic device layout pattern

Disclosed is a method for an electro-migration optimized ratio-logic device layout pattern. Benefits include improved performance.

Background

              Ratio-logic devices, such as a NOR gate, consist of two inverters with outputs that are tied together at a certain width ratio between the n- and p-transistors, to enable the correct logic operation. The typical layout pattern comprises two inverters that are built separately, but have the outputs connected through metal layers (see Figure 1).

              Ratio-logic gates have a contention current larger and may last longer than normal static CMOS gates by several times. This contention current is caused by the p-transistor of one inverter being on at the same time as the n-transistor of the second inverter for certain logic input combinations. Although these devices are used in pulsed environments, and the contention current is momentary, it is still very substantial compared to other CMOS.

              The conventional method includes two invertors making up the NOR gate connected by a single wire. The requirements for this wire have become more stringent due to process shrinks. A simple widening of the wire to the required widths results in significant added area and capacitance, which causes a reduction in speed. In some instances, this fix is not possible because of wire width limits and the straps over the contacts are not wide enough to handle the current.

              A second fix is to route upper level metals over the center of both p- and n-diffusion. This fix adds at least two upper-level metals. These metals also add ext...