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Method for static processor caching for mission-critical processes

IP.com Disclosure Number: IPCOM000008933D
Publication Date: 2002-Jul-24
Document File: 4 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for static processor caching for mission-critical processes. Benefits include improved performance through less instruction cache misses.

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Method for static processor caching for mission-critical processes

Disclosed is a method for static processor caching for mission-critical processes. Benefits include improved performance through less instruction cache misses.

Background

              An on-die cache miss requires that the processor swap out a cache line with the much slower memory. Swapping out cache lines for performance critical applications is a significant performance issue. This operation can be especially expensive if the application frequently runs the instructions that the processor swapped to memory.

              Usually high-end servers only run one application. The processors contained in systems can now be specialized to run these performance critical applications through having the mission critical instructions in the processors static cache. Other applications running on the same processors could have some degradation in performance due to the loss of flexible cache. This loss could easily be fixed in multi-way systems using processor affinity.

Description

              The disclosed method describes a new type of processor caching scheme with dynamic and static cache. The method adds a static on-die instruction cache to hold performance critical instructions. The static cache consists of the same type of transistors as the dynamic cache and works at the same speed. Boot-up of the processor pulls preassigned instructions from memory into a semi-permanent section of the cache on the processor. The processor is specialized for a particular application or operating system (OS). The instructions held within this static processor cache are never swapped out into memory. The processor constantly checks two instruction translation look-aside buffers (ITLBs) in parallel:

·        The normal ITLB which includes the on-die dynamic cache of the logical processor

·        The fixed ITLB, which only covers the on-die, fixed cache of the processor

              The performance critical instruction can always be found in the static cache at a constant location. This approach greatly reduces the ITLB misses for mission critical processes on an application or OS.

              This idea does not replace the dynamic instruction cache but augments it. The processor is specialized for the application, which has instructions stored in the static cache. The static cache ensures that nonpriority parts of the application and other applications do not evict the lines of mission critical processes within...