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A METHOD FOR EFFICIENT NONLINEAR TRANSIENT ANALYSIS

IP.com Disclosure Number: IPCOM000008996D
Original Publication Date: 1999-Jan-01
Included in the Prior Art Database: 2002-Jul-30

Publishing Venue

Motorola

Related People

Tuyen V. Nguyen: AUTHOR

Abstract

This paper presents a stable quasi-explicit inte- gration for nonlinear transient analysis. This algo- rithm is a generalization of the Adaptively Controlled Explicit Simulation (ACES) algorithm [l]. The method retains the efficiency and numeri- cal stability properties of ACES. Moreover, the method is flexible in the sense that it can accommo- date general nonlinear device models and it can also exploit simple device models (such as piecewise polynomial) to provide significant efficiency improvement. Traditional implicit techniques are general and accurate, but not flexible enough to exploit simple models for significant gain in effi- ciency. More recently developed fast timing simula- tion algorithms achieve significant speedups by employing simple piecewise linear or piecewise quadratic models. However, these algorithms are not sufficiently general to accommodate more detailed models to capture important physical effects without significant degradation in simulation efficiency.

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MOTOROLA Technical Developments

A METHOD FOR EFFICIENT NONLINEAR TRANSIENT ANALYSIS

by Tuyen V. Nguyen

ABSTRACT

  This paper presents a stable quasi-explicit inte- gration for nonlinear transient analysis. This algo- rithm is a generalization of the Adaptively Controlled Explicit Simulation (ACES) algorithm
[l]. The method retains the efficiency and numeri- cal stability properties of ACES. Moreover, the method is flexible in the sense that it can accommo- date general nonlinear device models and it can also exploit simple device models (such as piecewise polynomial) to provide significant efficiency improvement. Traditional implicit techniques are general and accurate, but not flexible enough to exploit simple models for significant gain in effi- ciency. More recently developed fast timing simula- tion algorithms achieve significant speedups by employing simple piecewise linear or piecewise quadratic models. However, these algorithms are not sufficiently general to accommodate more detailed models to capture important physical effects without significant degradation in simulation efficiency.

INTRODUCTION

  With design trends continuously moving towards higher clock speed, higher density and higher levels of integration on chip, there arise two

conflicting requirements: the need to move to higher levels of design abstraction to manage design com- plexity, and at the same time the need to capture lower level physical effects to ensure working designs. The method presented in this paper is intended to provide a flexible transient simulation capability that can improve significantly simulation throughout in terms of turn around simulation time and circuit size. This capability is an important component in the verification strategy of the present and future complex integrated circuits.

  Numerous techniques have been developed to address this problem [l]-[lo]. In general, the effi- ciency of a nonlinear transient analysis depends upon the simulation algorithm, the complexity of the device models and the complexity of circuit topolo- gy. For full chip simulation, the reduced order mod- eling of large linear interconnect circuits will also have a significant impact on the simulation efftcien- cy. However, this is a separate problem that has been discussed elsewhere [13][14]. This paper will focus on the problem of 'accurate and efficient tran- sient simulation of large scale integrated circuits and systems, which include, general nonlinear device models. Note that linear circuit elements as well as reduced order multi-port models of large linear cir- cuits are also included.

  There have been two major approaches in tim- ing simulation to improve the efficiency of transient simulation. Common to all approaches is the use of circuit partitioning and event driven simulation to exploit the spatial sparcity and the temporal latency of large circuits. One approach is to simplify circuit topology to a set of primitives, especially for MOS circuits,...