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A THERMALLY ENHANCED 2-LAYER PBGA SUBSTRATE DESIGN

IP.com Disclosure Number: IPCOM000009041D
Original Publication Date: 1999-Jan-01
Included in the Prior Art Database: 2002-Aug-02
Document File: 1 page(s) / 45K

Publishing Venue

Motorola

Related People

L. Michael Eyman: AUTHOR [+2]

Abstract

For typical plastic ball grid array (PBGA) pack- ages, 90% of die power dissipation is conducted downward, through the package substrate, into the printed wiring board. Unfortunately, two-layer PBGA substrates often lack sufficient copper cover- age and trace orientation to effectively spread power generated by the die. As a result, thermal perfor- mance suffers.

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MOlVROLA Technical Developments

A THERMALLY ENHANCED 2-LAYER PBGA SUBSTRATE DESIGN

by L. Michael Eyman and Zane Johnson

PROBLEM STATEMENT

  For typical plastic ball grid array (PBGA) pack- ages, 90% of die power dissipation is conducted downward, through the package substrate, into the printed wiring board. Unfortunately, two-layer PBGA substrates often lack sufficient copper cover- age and trace orientation to effectively spread power generated by the die. As a result, thermal perfor- mance suffers.

SPECIFIC CLAIMS

Four to eight copper traces running from the die attachment flag to the substrate edge enhance lateral

heat spreading. Enhancing the lateral heat spreading improves thermal performance. Adding these traces to the top and bottom sides of the substrate improves performance even more. These traces con- stitute a no-fuss, no-cost integral heat spreader that is particularly effective in perimeter PBGA designs. Unlike conventional heat sinks, the traces have no adverse effects on board-level solder joint reliability.

  By computational fluid dynamics simulation of the 196-lead mold array process PBGA package, the thermal traces reduce theta-JA by 14%.

10% of die power

Fig. 1

thermal trace (typ.)

Fig. 2

251 .hnuaq 1999

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