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Browse Prior Art Database

SENSING CIRCUIT AND METHOD FOR FLASH MEMORY

IP.com Disclosure Number: IPCOM000009052D
Original Publication Date: 1999-Jan-01
Included in the Prior Art Database: 2002-Aug-05
Document File: 3 page(s) / 116K

Publishing Venue

Motorola

Related People

Thomas Bushey: AUTHOR [+3]

Abstract

All memory cell arrays utilize either a voltage or current sense method, in one form or another, to determine the memory bit cell state. This electrical state is then propagated to the final buffer stage through two or more cascaded amplifier stages while meeting or exceeding the imposed design con- straints, such as read access time, power dissipation and die area.

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M-LA Technical Developments

SENSING CIRCUIT AND METHOD FOR FLASH MEMORY

by Thomas Bushey, James Caravella and Jeremy Moore

BACKGROUND

  All memory cell arrays utilize either a voltage or current sense method, in one form or another, to determine the memory bit cell state. This electrical state is then propagated to the final buffer stage through two or more cascaded amplifier stages while meeting or exceeding the imposed design con- straints, such as read access time, power dissipation and die area.

PROBLEM

  In determining the memory bit cell state, a rela- tively large current is switched onto the selected bit- line to initially charge the parasitic bitline capaci- tance. This large current is typically forced to flow through a P channel current mirror which leads to degradation in overall switching performance and may result in false reads due to large bitline tail cur- rent present when the pre-charge cycle is completed.

SOLUTION

  If the large surge current required to charge the bitline capacitance is shunted away from the P chan- nel current mirror during the pre-charge cycle, then the current mirror can be biased at approximately an operating point consistent with the memory cell read operation. One such circuit that can satisfy this

requirement is shown in Figure 1. For this circuit, a current sense method is employed to sense the mem- ory bit cell state. During the pre-charge cycle N channel transistors, M98, Ml09 and Ml47 source the surge current necessary to charge up the bitline capacitance. In addition, N channel transistor M98 determines the gate-source potential for P channel current mirror transistor, M112. Subsequently, the sa-pre signal transitions to a logic...