Browse Prior Art Database

SCHEMATIC BASED MAPPER

IP.com Disclosure Number: IPCOM000009053D
Original Publication Date: 1999-Jan-01
Included in the Prior Art Database: 2002-Aug-05
Document File: 5 page(s) / 231K

Publishing Venue

Motorola

Related People

Steven Calvo: AUTHOR [+4]

Abstract

This paper outlines the scheme used to imple- ment a schematic based mapper. The mapper is a translation tool that allows the user to specify map- ping rules that allow "a network of objects" (such as a logic circuit; as represented by a netlist) to be replaced with an alternative configuration of net- worked objects.

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M MO7VRO&A Technical Developments

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SCHEMATIC BASED MAPPER

by Steven Calvo, Arkell Rasiah, Rhys Sportmann and Matthew Taylor

INTRODUCTION

  This paper outlines the scheme used to imple- ment a schematic based mapper. The mapper is a translation tool that allows the user to specify map- ping rules that allow "a network of objects" (such as a logic circuit; as represented by a netlist) to be replaced with an alternative configuration of net- worked objects.

  This mapping scheme is required to search and replace networked objects within a larger network of objects. When applied to logic circuits, this tool can function as a technology mapper, logic optimiz- er and/or netlist translator.

  As its name suggests, this tool can be used for translating designs between different target technolo- gies. This has direct application in the synthesis flow of FPGAs, and is commonly referred to as technolo-

gy mapping.

  The description of this tool, its operation and design based on a working prototype of a tool known as the XNF (Xilinx Netlist Format[l]) trans- lator [2]. This translator was required to retarget any design described using XNF library components to a design using the Motorola Programmable Array (MPA) library.

DESCRIPTION

The mapper is a tool that:
1. Reads in a netlist file in the *net format.
2. Applies the mapping rules as specified by the rules files (*.mrf) and its accompaning macro speci- fications (*.net tiles)

3. Writes out the mapped design to the *net netlist (proprietary netlist format).

The software composition of the schematic based mapper is per Figure 1,

Thedesign
*.nat

.._

mapped

design.

*.net

'.mrf $Fsp' I *.net

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Fig. 1 Mapper Composition

289 Januarj 1999

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MO7VROLA Technical Developments

  The netlist reader is responsible for parsing a netlist file and populating the mapper's internal netlist data structure (C++ class), known as the internal netlist database (NDB). It supports the reading in of hierarchical netlists in multiple files, Also the netlist reader can be easily adapted to fea- ture support for various file formats. Netlist check- ing involves checking the integrity of the netlist
(e.g. valid net connectivity, no floating ports). Sorting of the netlist facilitates the mapping process, which performs mapping of the netlist according to five rules:

1. One to None: Component is ignored
2. One IO One (I-I): This mapping method is simply implemented by a scheme that does the replacement of an instance's type and the names of its ports.

3. One fo Many (I-M): This mapping is imple- mented as a "flattening" process.

  4. Many to One (M-l): This mapping is imple- mented by a novel search and replace mapping scheme.

  5. Many fo Many (M-M): This implemented as the combination of (M-l) and (1-M) mapping methods.A focal part of the mapper is a rules file. Note that it is the mappings that
ultimately describe the functionality of the mapper
e.g. logic optimi...