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A DIGITAL METHOD OF CONTROLLING ADAPT MODE AND DETECTING PHASE LOCK IN A FREQUENCY SYNTHESIZER

IP.com Disclosure Number: IPCOM000009074D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-06
Document File: 3 page(s) / 169K

Publishing Venue

Motorola

Related People

Joseph Charaska: AUTHOR

Abstract

A method is presented which describes how one can detect phase lock in a frequency synthesizer and use it to automatically switch from adaptive mode to normal operating mode. The accuracy of this method is controlled by two design variables, time delay and the maximum count in a digital counter. The resulting circuit is compatible with existing and future large scale integrated circuit technologies.

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MOTOROLA Technical Developments

A DIGITAL METHOD OF CONTROLLING ADAPT MODE AND DETECTING PHASE LOCK IN A FREQUENCY SYNTHESIZER

by Joseph Charaska

ABSTRACT

  A method is presented which describes how one can detect phase lock in a frequency synthesizer and use it to automatically switch from adaptive mode to normal operating mode. The accuracy of this method is controlled by two design variables, time delay and the maximum count in a digital counter. The resulting circuit is compatible with existing and future large scale integrated circuit technologies.

BACKGROUND

  A frequency synthesizer (also referred to as a phase locked loop) is the common group of circuit used in communications products for ~generating a stable radio frequency signal, which is needed for

modulating and demodulating a radio frequency car- rier signal (refer to Figure 1). The frequency syn- thesizer circuit uses feedback to compare the phase of a reference oscillator (Fref) to the phase of a high frequency voltage controlled oscillator (Fvco). The output of the phase comparator, along with the charge pump and loop filter circuits, drives the phase difference between the Fref/R and Fvco/N signals to a minimum by controlling the VCO steer- ing line. The frequency at which the comparison is performed is usually lower than either the reference oscillator's frequency or the voltage controlled oscillator's frequency. The phase detector inputs are preceded by divider circuits (programmable coun- ters) which allow numerous frequencies to be syn- thesized from a single circuit by changing the num- ber which is programmed into the divider circuits.

Fig. 1 Simplified Block Diagram

  The phase comparator is a key circuit inside the from low to high, then both the Up and Dn signals synthesizer. The function of the phase comparator will transition from high to low after a short delay. is to convert the Fr and Fv signals into series of Conversely, when the rising edge of Fv arrives pulses which cause the charge pump to either source before the rising edge of Fr, first the Dn signal will or sink current (refer to Figure 2). When the rising transition from low to high, then both the Up and edge of Fr arrives before the rising edge of Fv, the Dn signals will transition from high to low after a Up signal will transition from low to high, and when short delay.
the Fv signal arrives the Dn signal will transition

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MOTOROLA Technical Developments

Fig. 2 Phase Comparator Timing Diagram

BASIC LOCK DETECTOR OPERATION

  Detecting a locked condition in frequency syn- thesizers has been accomplished by using compara- tors on the VCO steering line signal (Vtune). The thresholds for declaring a locked condition are typi- cal between (Vcc-Vd) < Vhme < Vd (where: Vcc = Supply Voltage, Vd = Voltage across a forward biased diode). In low voltage synthesizer designs, Vcc = 2.7 V, and Vd = 0.94 V (at -4...