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Method for synchronizing high-frequency outputs of multiple integrated on-chip PLLs by means of phase-detection shadowing

IP.com Disclosure Number: IPCOM000009101D
Publication Date: 2002-Aug-07
Document File: 4 page(s) / 128K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for synchronizing high-frequency outputs of multiple integrated on-chip phase-locked loops (PLLs) by means of phase-detection shadowing. Benefits include improved performance, an improved design environment, and an improved test environment.

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Method for synchronizing high-frequency outputs of multiple integrated on-chip PLLs by means of phase-detection shadowing

Disclosed is a method for synchronizing high-frequency outputs of multiple integrated on-chip phase-locked loops (PLLs) by means of phase-detection shadowing. Benefits include improved performance, an improved design environment, and an improved test environment.

Background

              The following terms are used below:

·        HostPLL: Generates clocks for the processor-side bus (PSB), system and local memory

·        CorePLL: Generates clock for the 3D-graphics core engine

·        Display-A/Display-B PLLs: Generates clocks for the two 2D engines

              In conventional functional operation, both synchronous and asynchronous data transfers occur between various clock domains. For example PSB and system memory are always synchronous, where as data transfers across 3D-core and 2D-core clocks are always treated as asynchronous. Due to the high transistor count of graphics and memory controller hubs (GMCHs), these chips must go through functional vector testing at specified speed (MHz) to guarantee defects per million (DPM). Testing parts reliably on the IC-tester requires that all the clock domains on the chip should be synchronous to ensure deterministic data transfers across them and avoid cycle-slippage issues.

              To facilitate synchronous transfers across clock domains, a definite phase relationship needs to be established between all the internal and external clocks. In addition, data transfer enable or mask signals are needed to control data transfer across different clock domains. These masking signals are used by logic added at the interface boundary of typically asynchronous clock domains to make them synchronous during the functional testing of the part.

              A typical implementation of the clock synchronizer circuit requires a masking signal relationship for clocks CLKA and CLKB, where CLKA frequency is 2 times the frequency of CLKB (see Figure 2). The easiest way to generate this masking signal is by sampling the lower frequency clock (CLKB) by the falling edge of high frequency clock (CLKA). This type of state-machine or phase-detection logic is free running and requires no special reset (see Figure 1). The output is valid as long as the phase/frequency relationship of CLKA and CLKB remains deterministic and the clock uncertainty window between CLKA and CLKB is less than half the period of CLKA (FreqCLKA > FreqCLKB).

              Conventional solutions include cascaded on-chip PLLs that require a lot of design effort. Validation is typically theoretical, using silicon results from other/prior projects.

              Other conventional solutions include a synchronized reset from the clock-domain of one PLL to the high-frequency VCO domain (>1 GHz) of a second PLL. These solutions are difficult to design and validate. Testing is complex and affects the functional mode. This approach is less flexible due to late product/testing requirements changes/additions.

Description

              The disclosed m...