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Method for ACIO performance testing

IP.com Disclosure Number: IPCOM000009102D
Publication Date: 2002-Aug-07
Document File: 3 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for ACIO buffer performance testing. Benefits include improved functionality, improved reliability, and improved test environment.

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Method for ACIO performance testing

Disclosed is a method for ACIO buffer performance testing. Benefits include improved functionality, improved reliability, and improved test environment.

Background

      Conventionally, buffer testing is comprised of several tasks, including:

·        Pin-leakage testing

·        AC tight-timing tests

·        Input voltage (VIX)

·        Output levels (VOX)

·        RCOMP coverage

              Several limiting factors affect the quality of the tests, including:

·        Limited tester speeds

·        Available number of tester channels

·        Limited vector memory depth to fit all patterns

·        Available number of testability hooks

·        Limited engineering resources to develop robust tests

              Sometimes, products take calculated defects per million (DPM) risks and tests such as AC tight timing and RCOMP are removed from the production test tapes to save test time.

Description

              The disclosed method is ACIO buffer performance testing. It consists of several components and subtasks, including:

·        NG_ACIO algorithm and tester user functions

·        IO Procmon method (tester user function with special register read-out pattern)

·        IO DFT state machine (drive programmed data, capture, compare, and flag results)

·        Buffer strength based data strobe delay generator (read/write register)

·        Slew rate based data strobe delay generator (read/write register)

·        Quad-strobe delay generator (programmable register)

·        NTL BIST test method

·        VIX BIST test method

·        VOX BIST test method

·        Test hooks for the receiver VREF, driver Z-tristate, and external strobes for non-SS interfaces

              The methodology is essentially a solution matrix integrated into one large test set using tester user functions, and following the NG_ACIO algorithm. Each subtest is independent and a complete test in itself as a DFT replacement to some traditional test. NG_ACIO finds the common factors, alleviates redundancies, reuses the DFT hooks, and optimizes all ingredients into one effective test methodology.

              The heart of the methodology on Si is the IODFT state machine that can be programmed to drive data on the buffer outputs. The buffer strength control, slew rate control, and driver tristate control hooks available for various tests are used. The signal integrity of output data can be precisely controlled for several factors, including:

·        Levels

·        Strength

·        Edge rate

·        Timing

              For receiver testing, this highly controlled signal can be treated as if coming from sophisticated external test equipment. Additionally, data and strobe buffers are trea...