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Method for a highly accurate, scalable, no-touch leakage built-in self-test

IP.com Disclosure Number: IPCOM000009103D
Publication Date: 2002-Aug-07
Document File: 2 page(s) / 37K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a highly accurate, scalable, no-touch leakage built-in self-test (NTL BIST). Benefits include improved test environment and improved reliability.

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Method for a highly accurate, scalable, no-touch leakage built-in self-test

Disclosed is a method for a highly accurate, scalable, no-touch leakage built-in self-test (NTL BIST). Benefits include improved test environment and improved reliability.

Background

              NTL BIST is a conventional test method used on multiple chipset products for pin-to-VCC, pin-to-ground, and pin-to-pin leakage testing without touching the device pins with a tester channel or external instrumentation. The physics behind the test is simple and well known. All of the published work uses boundary scan as an implementation vehicle. However, detailed analysis verifies that this approach has accuracy, efficiency, or scalability issues.

              The conventional leakage testing with tester instrumentation provides 1nA resolution on a typical 1µA range. Boundary scan methods are at least 15X to 30X poorer in resolution, and, even theoretically, do not achieve the conventional tester accuracy of 1nA or less. This accuracy gap is widening as test quality requirements become more stringent with improved processes.

Description

              The disclosed method is NTL BIST using a programmable state machine multiplexed to the buffer I/O and control signals. The state machine is typically preexisting as the standard IODFT state machine on most interfaces to support various other buffer tests (see Figure 1). Buffer drivers charge the node to a known voltage state. Buffer input receivers operate as a high-frequency comparator sampler. Recei...