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Method for a slew-rate based data strobe delay generator

IP.com Disclosure Number: IPCOM000009105D
Publication Date: 2002-Aug-07
Document File: 2 page(s) / 57K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a slew-rate based data strobe delay generator. Benefits include improved functionality and an improved test environment.

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Method for a slew-rate based data strobe delay generator

Disclosed is a method for a slew-rate based data strobe delay generator. Benefits include improved functionality and an improved test environment.

Description

              The disclosed method uses a slew-rate based data strobe delay generator for stressing the buffer timings during AC timing tests, and input voltage built-in self-test (VIX BIST).

              Due to the way bus timings are defined, the method is slow data/fast strobe and fast data/slow strobe. Buffer slew rates are controlled, typically, via 5 bit registers that are programmed based on certain on-chip state machines, following fixed algorithms. The goal is to keep the slew rates in the middle of the minimum-to-maximum specification (typically, 1 V/ns to 4 V/ns). Buffers are designed and tested to meet these specifications.

              To realize the slew-rate based data strobe delay generator, two steps are required.

·        Separate routing of data and strobe buffers’ slew rate controls (already available in most cases)

·        External bit programmability of slew rate control registers, bypassing any functional state machine controls from the core

              With the availability of these two design for testability (DFT) features, a device can be forced to artificially function as a slower or faster part, on data or strobe, precisely for certain cycles. Typically, on a 400-MHz bus, measuring at VREF specification level, timing delays of the order of 325 ps can be realized. As busses scale upwards, granularity...