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Method for a highly accurate, scalable, receiver input voltage built-in self-test

IP.com Disclosure Number: IPCOM000009106D
Publication Date: 2002-Aug-07
Document File: 4 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a highly accurate, scalable, receiver input voltage built-in self-test (VIX BIST). Benefits include improved functionality and an improved test environment.

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Method for a highly accurate, scalable, receiver input voltage built-in self-test

Disclosed is a method for a highly accurate, scalable, receiver input voltage built-in self-test (VIX BIST). Benefits include improved functionality and an improved test environment.

Background

              In conventional VIX (VIL and VIH) testing, a tester drives high-to-low and low-to-high transitions into device receivers while the VREF level is externally set at VIL or VIH specification levels respectively. Defective receivers violating the specification are detected. This method requires special tester pattern development and physically requires many tester driver channels (typically, equal to the number of receivers being tested, unless channels are shared). XOR chains can also be used for VIX testing. Captured data must be strobed for pass/fail by additional tester channels using device under test (DUT) outputs on some other interface.

Description

              The disclosed method uses a receivers input voltage built in self-test (VIX BIST). It is a highly accurate, efficient, low cost, and scalable test method being employed on multiple chipset products for receivers input voltage (low and high) testing without touching the device pins with a tester channel or external instrumentation. This approach saves test time and paves the way to multiple die sort/class testing on very high pin count devices.

              VIX BIST applies the same physics as used in conventional VIX testing. However, an on-die IODFT state machine is used for driving and comparing the transitions in place of the traditional Tester. High-to-low and low-to-high transactions are driven into the DUT receivers using DUT outputs, and the captured data in the receivers is analyzed by the same IODFT state machine detecting pass/fail. No external pattern generation is required, and the test takes only few cycles at full functional speed. On-die VREF levels generation is intentionally avoided because it calls for extensive DFT that might not be reliable unless calibrated. An external VREF source (tester channel) is used.

              VIX BIST consists of a programmable state machine (usually pre-existing as standard IODFT state machine on most interfaces to support various other buffer tests) multiplexed to the buffer I/Os and control signals. Receiver strobes can be internal (such as in source synchronous interfaces) or external (such as in common clock interfaces). The VIX BIST state machine is a fully reusable. It can be instantiated as a standard DFT block on any interface for any number of instances in a chip. Concurrent testing is possible and is recom...