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Method for a highly accurate, scalable, buffer output voltage level built-in self-test

IP.com Disclosure Number: IPCOM000009107D
Publication Date: 2002-Aug-07
Document File: 3 page(s) / 108K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a highly accurate, scalable, buffer output voltage level built-in self-test (VOX BIST). Benefits include improved functionality and an improved test environment.

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Method for a highly accurate, scalable, buffer output voltage level built-in self-test

Disclosed is a method for a highly accurate, scalable, buffer output voltage level built-in self-test (VOX BIST). Benefits include improved functionality and an improved test environment.

Background

              In conventional VOX (VOL and VOH) testing, The DUT buffer drives high-to-low and low-to-high transitions into a tester receiver load (DC load specification) while the tester receiver VREF level is set at the specified VOL or VOH level. Such driving usually results in ringing (overshoot or undershoot). Tester receivers wait for a certain settling time. The data from the DUT is strobed to see if it is meeting the VOL or VOH specs. A weak buffer driver under test may not be able to pull-up to the VOH level or pull down to the VOL level and a defect is detected. Similarly, an excessively strong buffer might create so much ringing that it cannot settle down before the device is strobed at the tester and is labeled as defective. This method requires special tester pattern development and physically requires many tester receiver channels (typically, equal to the number of buffer drivers being tested, unless channels are shared).

Description

              The disclosed method uses a buffer output voltage level built-in self-test (VOX BIST). It is a highly accurate, efficient, low cost, and scalable test method being used on multiple chipset products for buffer drivers output voltage (low and high) testing without touching the device pins with a tester channel or external instrumentation. This approach saves test time and paves the way to multiple die sort/class testing on very-high pin count devices.

              VOX BIST utilizes the same physics used in conventional VOX testing. However, an on-die IODFT state machine is used for driving and comparing the transitions in place of the conventional tester. High-to-low and low-to-high transactions are driven out of the DUT buffer drivers and chip’s own receivers are used in place of tester receivers to capture and analyze data. The IODFT state machine determines pass/fail results. No external pattern generation is required. The test takes only few cycles at full functional speed. On-die VREF levels generation is intentionally avoided because it calls for extensive design for testability (DFT) that might not be reliable unless calibrated. An external VREF source (tester channel) is used (much higher return on investment and reliability).

              VOX BIST consists of a programmable state machine (usually pre-existing as standard IODFT state machine on most interfaces to support various other buffer tests) multiplexed (muxed) to the buffer I/Os and control signals. Buffer receiver strobes can be internal (such as source synchronous interfaces) or external (such as common clock interfaces). The VOX BIST state machine is a fully reusable, can be instantiated as a standard DFT block on any interface, any number of ins...