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Method for memory-module thermal protection

IP.com Disclosure Number: IPCOM000009112D
Publication Date: 2002-Aug-07
Document File: 7 page(s) / 161K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for memory-module thermal protection. Benefits include improved functionality and improved thermal performance.

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Method for memory-module thermal protection

Disclosed is a method for memory-module thermal protection. Benefits include improved functionality and improved thermal performance.

Background

              As memory bandwidths increase rapidly and DRAM core voltages decrease at a much lower rate, thermal impact to the DRAMs is critical.

              Increased memory bandwidth and increased capacity requirements are driving the requirement to include a buffer chip on a high-speed memory module. A thermal sensor and control logic detect and report over-heating to the memory controller or processor that can protect the “hot” memory module from being damaged.

              For the past 15 years, memory subsystems have relied on a stub-bus topology with memory modules (DIMMs) that plug into connectors on a memory channel. Each DIMM adds a short electrical stub to the memory bus. Simulations indicate that for applications of 2-4 DIMMs per channel, the stub bus technology reaches a maximum bandwidth of 400-533 MT/s or 3.2-4.2 GB/s for an 8-byte wide DIMM. This memory bus technology is conventionally used with PC100, PC133, DDR-I, and DDR-II. Getting to the next significant level, 667 MT/s and beyond is difficult, if not impossible, with the stub-bus technology.

              As memory bandwidth requirements increase above 3.2-4.2 GB/s per DIMM channel, point-to-point signaling technology is used, building upon technology previously developed for scalability port, Infiniband architecture, and other point-to-point busses. A point-to-point memory bus requires a buffer chip on each memory module to receive the incoming signal and drive it to the next receiver in a daisy-chain fashion (see Figure 1).

              With the fully buffered memory module, the connection between the memory controller and the first DIMM, and between each pair of DIMMs, is point-to-point. The buffer indicated in Figure 1 may actually be implemented as one, two or three devices. This thermal protection mechanism could be implemented on any or all of these buffer devices. For example, the three devices could be one command/address buffer, and two data buffers. For the purpose of this disclosure, only a single buffer chip for each memory module is considered.

              Signaling at maximum transfer rates for an extended time can be destructive to DRAM components on the memory module due to overheating. Factors that can affect DRAM thermals include:

·        Ambient temperature

·        Active cooling

·        Airflow

·        DRAM package

·        Activity level

·        Process

·        Operational voltage

              Typically, short bursts of high DRAM activity are acceptable but could cause damage if the high-activity level is sustained over longer time periods. Most applications do not cause the DRAM activity rate to rise to a point where thermal damage could occur, but it is possible for such an event to occur. In addition, a destructive virus could be unleashed with the intent of causing thermal damage to the memory module. Ideally, the memory subsystem should run with no limitation to data transfer rates, except...