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Extending the PAM-Type Memory Region Size by Using Processor Cache Attributes

IP.com Disclosure Number: IPCOM000009114D
Publication Date: 2002-Aug-07
Document File: 2 page(s) / 42K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a processors write protect cache attribute to emulate PAM-style memory region behavior. Benefits include extending the size of the PAM-type memory region that is available on the platform.

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Extending the PAM-Type Memory Region Size by Using Processor Cache Attributes

Disclosed is a method that uses a processor’s “write protect” cache attribute to emulate PAM-style memory region behavior. Benefits include extending the size of the PAM-type memory region that is available on the platform.

Background

The memory controller chipset allows programmable attributes on memory below 1MB (C, D, E, & F segments). This memory region is commonly referred to as PAM. Memory attribute control within this region is available in various sizes, depending on memory controller capability.

Typically, the 256KB of PAM-type area on the chipset memory controller is occupied by Option ROM code, such as Video, LAN, or SCSI (at 128KB), and System BIOS runtime code (at 128KB). Other runtime critical data is necessary for the successful operation of the platform, but must be rejected from the final Pre-OS ROM image due to runtime size constraints. The PAM-type area holds critical data that is necessary for the loading of the OS drivers (Video drivers, SCSI drivers, Network drivers, etc). The normal usage of the PAM attribute is “read enable” after shadowing the Option ROM’s and System BIOS runtime code; this prevents writes from occurring in this memory area.

Pre-OS software (System BIOS & EFI modules) runtime code is normally present on the non-memory interface and during the initialization process. After the needed runtime code is completely shadowed into memory, the attributes for that me...