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Redirecting Bus Master Cycles to Non-Memory Locations for Debug Purposes

IP.com Disclosure Number: IPCOM000009115D
Publication Date: 2002-Aug-07
Document File: 3 page(s) / 98K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that redirects bus master cycles to the non-physical memory locations of a debug card for debugging.

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Redirecting Bus Master Cycles to Non-Memory Locations for Debug Purposes

Disclosed is a method that redirects bus master cycles to the non-physical memory locations of a debug card for debugging.

General Description

In the disclosed method, AGP aperture addresses are mapped into main memory in 4KB pages via the Graphics Address Re-mapping Table (GART). GART enables memory addresses to be mapped in a contiguous view. AGP_base and AGP_size are located in APBASE and APSIZE, respectively, which reside in the PCI Config space of the chipset. The system BIOS sets APBASE and APSIZE prior to using the GART registers. APBASE can later be modified by the OS to change the aperture base. 

The ATTBASE register points to the base of the GART. Each 32-bit entry in Table 1 translates one 4KB page of system memory:

Bit

Description

31:12

MEMPGN:

This fields contains bits 31:12 of the main memory address associated with the GART address for this entry

11:1

Reserved

0

VALID:

Set to 1 if the contents of the entry contain a valid address, otherwise reset to 0

Table 1. Sizes and formats of the translation table entries

In the disclosed method, these entries are used to redirect the bus master cycles to an alternative source of memory for debug purposes (see Figure 1).

Table 2 shows the actual memory address on every 4K boundary; for this usage model, only entries that are valid or used need a valid memory address value, otherwise the GART table entries can be made invalid during the Pre-OS or debug...