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EEPROM RELIABILITY PREDICTION SCREEN USING VARIABLE BITLINE VOLTAGE IN BULK PROGRAM MODE

IP.com Disclosure Number: IPCOM000009139D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-09
Document File: 4 page(s) / 157K

Publishing Venue

Motorola

Related People

Steven Donnelly: AUTHOR [+3]

Abstract

Testing NVM arrays is very time consuming and costly, especially when trying to eliminate weak devices which could become early life failures. This prediction screen will identify potential unreliable bits in the EEPROM array in a time effective and cost effective maturer. The screen uses a combination of on-chip hardware and external tester control utilizing real time analysis of Vt distributions and including a novel binning algorithm to each die under test.

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0 M

MO7WROLA Technical Developments

EEPROM RELIABILITY PREDICTION SCREEN US;ING VARIABLE BITLINE VOLTAGE IN BULK PROGRAM MODE

by Steven Donnelly, Christian Dodd and Andrew Birnie

ABSTRACT

  Testing NVM arrays is very time consuming and costly, especially when trying to eliminate weak devices which could become early life failures. This prediction screen will identify potential unreliable bits in the EEPROM array in a time effective and cost effective maturer. The screen uses a combination of on-chip hardware and external tester control utilizing real time analysis of Vt distributions and including a novel binning algorithm to each die under test.

TECHNIQUE

Figure 1 shows a simplified diagram of an EEP- ROM cell. The rate and magnitude of programming

the cell is determined by the electric (E) field across the double polysilicon layered structure. The electric field is controlled by the two applied voltages, Vcontrol gate and Vdrain. ~ Due to the maximum sus- tainable voltages on silicon', both positive and negative voltages are used to generate the necessary E-field. By controlling Vdrain via the bitline voltage, the strength of the E-field is modulated. Such control of the bitline is achieved in this design, by the VPEX control logic, which channels the external Vdd supply to the selected bitlines.

"control gate

V source

2nd polysilicon - control gate

A Si substrate L

Fig. 1 Cross Sectional Diagram of a Simple Double Polysilicon Thin Oxide EEPROM Cell

0 Maomla, Inc. 1999 84 June 1999

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MOTOROLA Technical Developments

vcontrol gate

V source

Vdrain

2nd polysilicon - control gate

Si substrate

Fig. 2 VPEX Control Logic Determines the Source of the Bitline Voltage-Either from the

Bitline Charge Pump (as in standard user mode) or from the Vdd Pad

  For a set bulk program time the response to a num- ber of program operations with various Vdd (i.e. bitline voltages) can be measured by means of a Vt distribu- tion. The shift of the Vt distribution under successive program operations would be controlled and optimized to highlight any abnormal cells. It is possible to use this technique to differentiate between 'good' and 'bad' EEPROM cells, where a 'bad' cell is a one that pro- grams differently, i.e. too low or too high a Vt shift for a given change in applied bitline voltage. These 'bad' cells have been shown to be highly likely to be early life reliability fails. Due to the exponential behavior of change of electron tunneling with E-field (and hence applied voltages and oxide thickness) this test is extremely sensitive to defects in the oxide and also to changes in the applied bitline voltage.

BINNING ALGORITHMS

  There are many possible binning algorithms for this test technique, two are presented here. The more traditional method of Figure 3a, shows the device can be binned based on the shift in Vt distribution caused

by the applied change in external voltage (V2-VI). Any o...