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CHARGE PUMP REGULATION FOR FAULT DETECTION IN HIGH VOLTAGE NON-VOLATILE MEMORY CIRCUITS

IP.com Disclosure Number: IPCOM000009141D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2002-Aug-09
Document File: 5 page(s) / 234K

Publishing Venue

Motorola

Related People

Christian Dodd: AUTHOR [+3]

Abstract

Currently the high voltage circuits in non- volatile memory designs are typically tested by per- forming lengthy program and erase sequences. Even with this technique, usually only gross faults are found as opposed to subtle fails, which do not cause logical 'stuck at' conditions but could later become reliability concerns or early life fails.

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MOTVROLA Technical Developments

CHARGE PUMP REGULATION FOR FAULT DETECTION IN HIGH VOLTAGE NON-VOLATILE MEMORY CIRCUITS

by Christian Dodd, Philippe Bauser and Steven Donnelly

PROBLEM STATEMENT

  Currently the high voltage circuits in non- volatile memory designs are typically tested by per- forming lengthy program and erase sequences. Even with this technique, usually only gross faults are found as opposed to subtle fails, which do not cause logical 'stuck at' conditions but could later become reliability concerns or early life fails.

  Provided the avalanche voltage, or parasitic devices do not clamp the charge pumps in normal operation, there is also no measure that there is a reliable margin between the worst case clamping voltage in the design and the voltage generated by the charge pump. More importantly, localized defects could cause premature voltage clamping or increased leakage but still allow the affected struc- ture to operate in a logical fashion. Provided the current load the defect represents is less than the current which the appropriate charge pump is capa- ble of supplying, then the defect may go undetected as the charge pump voltage will remain the same. For this class of defect, if the charge pump voltage is unaffected, no significant differences in non-volatile cell performance may be detected with conventional production test techniques.

  Currently STOP mode current measurements are made in the lowest power mode and provide an excellent method for screening defective standard low voltage logic from both a reliability and fnnc- tional perspective. Entering into the lowest power mode typically involves disabling all device clocks,

including those for the non-volatile memory module and charge pumps, and disabling all analogue cir- cuits. In this state, no high voltages are generated to check significant portions of the non-volatile array
e.g. high voltage switches, row / column drivers, row / column decoders, ~ high voltage data latches etc. It is obvious that conventional low power qui- escent current measurements do not provide a par- ticularly effective screen for significant section of the array, especially the high voltage sections as the charge pumps are normally disabled during the mea- surement and no current flows through any defects present.

  With current test methodologies for non-volatile memories tending towards Design For Test (DFT) and Self Test, the use of low cost test systems will become critical. It is evident that an efficient and fast method for performing quiescent current mea- surements on a non-volatile memory array could be extremely useful. It would allow screening defects that not only cover the logical 'stuck-at' faults but also potential 'leaky' defects which still behave cor- rectly in the high voltage,portion of the array.

SOLUTION

  In normal operating modes for many non- volatile memory devices; a local oscillator provides the charge pump clocks., In test mode, however, the clock can...